ADV7183AKST Analog Devices Inc, ADV7183AKST Datasheet - Page 16

• Manufacturer Part Number: ADV7183AKST
• Description: IC VIDEO DECODER NTSC 80-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7183AKST

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADV7183A
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
POWER-SAVE MODES
Power-Down
PDBP, Address 0x0F [2]
There are two ways to shut down the digital core of the
ADV7183A: a pin ( PWRDN ) and a bit (PWRDN see below).
The PDBP controls which of the two has the higher priority.
The default is to give the pin ( PWRDN ) priority. This allows the
user to have the ADV7183A powered down by default.
Table 11. PDBP Function
PDBP
0 (default)
1
PWRDN, Address 0x0F [5]
Setting the PWRDN bit switches the ADV7183A into a chip-
wide power-down mode. The power-down stops the clock from
entering the digital section of the chip, thereby freezing its
operation. No I
PWRDN bit also affects the analog blocks and switches them
into low current modes. The I
and remains operational in power-down mode.
The ADV7183A leaves the power-down state if the PWRDN
bit is set to 0 (via I
RESET pin.
PDBP must be set to 1 for the PWRDN bit to power down the
ADV7183A.
Table 12. PWRDN Function
PWRDN
0 (default)
1
ADC Power-Down Control
The ADV7183A contains three 10-bit ADCs (ADC0, ADC1,
and ADC2). If required, it is possible to power down each ADC
individually.
When should the ADCs be powered down?
•
•
CVBS mode. ADC1 and ADC2 should be powered down
to save on power consumption.
S-Video mode. ADC2 should be powered down to save on
power consumption.
Description
Digital core power controlled by the PWRDN pin
(bit is disregarded).
Bit has priority (pin is disregarded).
2
Chip operational.
ADV7183A in chip-wide power-down.
Description
C bits are lost during power-down. The
2
C), or if the overall part is reset using the
2
C interface itself is unaffected,
Rev. B | Page 16 of 104
PWRDN_ADC_0, Address 0x3A [3]
Table 13. PWRDN_ADC_0 Function
PWRDN_ADC_0
0 (default)
1
PWRDN_ADC_1, Address 0x3A [2]
Table 14. PWRDN_ADC_1 Function
PWRDN_ADC_1
0 (default)
1
PWRDN_ADC_2, Address 0x3A [1]
Table 15. PWRDN_ADC_2 Function
PWRDN_ADC_2
0 (default)
1
RESET CONTROL
Chip Reset (RES), Address 0x0F [7]
Setting this bit, equivalent to controlling the RESET pin on the
ADV7183A, issues a full chip reset. All I
their default values. (Some register bits do not have a reset value
specified. They keep their last written value. Those bits are
marked as having a reset value of x in the register table.) After
the reset sequence, the part immediately starts to acquire the
incoming video signal.
Notes
•
•
•
Table 16. RES Function
RES
0 (default)
1
After setting the RES bit (or initiating a reset via the pin),
the part returns to the default mode of operation with
respect to its primary mode of operation. All I
loaded with their default values, making this bit self-
clearing.
Executing a software reset takes approximately 2 ms.
However, it is recommended to wait 5 ms before any
further I
The I
condition on the ninth clock cycle when chip reset is
implemented. See the MPU Port Description section.
2
C master controller receives a no acknowledge
2
C writes are performed.
Description
ADC normal operation.
Power down ADC 1.
Description
ADC normal operation.
Power down ADC 2.
Description
Normal operation.
Start reset sequence.
ADC normal operation.
Power down ADC 0.
Description
2
C registers get reset to
2
C bits are