STA016A STMicroelectronics, STA016A Datasheet

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... Generic features – Faster browsing, feed forward and rewind ca- pabilities – long file name support 1.1 APPLICATIONS AUDIO CD PLAYERS MULTIMEDIA PLAYERS CD-ROM PLAYERS CAR RADIO PLAYERS STA016A PRODUCT PREVIEW TQFP64 Package TQFP64 2 S AND REV. 1 1/43 ...

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... DESCRIPTION The STA016A is a single chip MPEG 1, 2 and 2.5 Layer III audio decoder with embedded CDROM decoding capability. It can be easily connected to most existing CDDSP devices via a software configurable serial link. A tipical application block diagram is show in Figure 1. The audio sources, for instance could be an external flash memory ...

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... DETECT. INPUT SELECTOR MMDSP CORE PCM OUTPUT - ISO9660 + JOLIET BUFFER - BCI - MP3 PLL REG BANK OSCK XTI 2 C bus. Besides that the GPSO interface can be STA016A MPEG 2.5 12 11.025 8 SECTOR BUFFER BCKO OUT SDO I/F LRCKO GPSO_CK GPSO_SDO GPSO OSC I/F ...

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... MCU -> STA016A: commands used to handle decoder operation and to ask for specific information like filename, filelength, sector raw data, etc. This flow will use I STA016A -> MCU: this channel is used to retrieve inquired information and to inform MCU that a CDDSP specific operation must be performed (like pick-up repositioning). This flow is based on I plus an additional interrupt signal in order to avoid time consuming polling techniques. MCU -> ...

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... I/O GPIODATA8 I/O GPIODATA9 I/O GPIODATA10 I/O GPIODATA11 I/O GPIODATA12 I/O GPIODATA13 I/O GPIODATA14 I/O GPIODATA15 STA016A Sourde/Dest From DSP From DSP From DSP From MCU From MCU From MCU To MCU From ADC From ADC From ADC To DAC To DAC To DAC To DAC/ADC ...

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... STA016A Table 5. PIN DESCRIPTION (continued) PIN Pin Name 60 STB 59 RQST 63 SCL 64 SDA 17 XTI 18 XTO 25 CLKOUT 15 -RESET 16 -TESTEN 40 FILT0 38 FILT1 39 PLL_VCC 41 PLL_GND 5 VDD_1 10 VDD_2 29 VDD_3 36 VDD_4 53 VDD_5 62 VDD_6 23 VCC_1 42 VCC_2 58 VCC_3 6 VSS_1 11 VSS_2 24 VSS_3 30 VSS_4 37 VSS_5 43 VSS_6 52 VSS_7 57 VSS_8 61 VSS_9 6/43 Type ...

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... Test Condition Leakage < Test Condition I = Xma ol Test Condition V = 0V; pin numbers and 26 Test Condition = 2.4V Sampling_freq 24 kHz Sampling_freq 32 kHz Sampling_freq 48 kHz STA016A Value 2.5 ± 0.25 3.3 ± 0.3 2.5 ± 0.25 Min. Typ. Max. Unit - - 2000 V Min. Typ. Max. Unit 0.2 ...

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... STA016A 5 HOST REGISTERS The following table gives a description of STA016A register list. The STA016A device includes 256 I scribed. The undocumented registers are reserved or unused. These registers must never be accessed (in Read or in Write mode). The Read-Only registers must never be written We can split the data flux in different time periods (see following diagram) meanwhile host registers can be read or written : DWT : During Whole Time (at any time during process) ...

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... PLL_SYSTEM_NDIV_42_5 0xEE 238 PLL_SYSTEM_XDIV_42_5 0xEF 239 PLL_SYSTEM_MDIV_42_5 0x66 102 OUTPUT_CONF 0x67 103 PCM_DIV 0x68 104 PCM_CONF 0x69 105 PCM_CROSS 0x66 102 OUTPUT_CONF 0x6A 106 GPSO_CONF 0x5A 90 INPUT_CONF 0x5B 91 I_AUDIO_CONFIG_1 0x5C 92 I_AUDIO_CONFIG_2 0x5D 93 I_AUDIO_CONFIG_3 STA016A Name Type When DWT DWT ...

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... STA016A Register function CDBSA_CONFIGURATION BSB_CONFIGURATION CD_CONFIGURATION 10/43 Hex Dec 0x5A 90 INPUT_CONF 0x5B 91 I_AUDIO_CONFIG_1 0x5C 92 I_AUDIO_CONFIG_2 0x5D 93 I_AUDIO_CONFIG_3 0x5E 94 I_AUDIO_CONFIG_4 0x5F 95 I_AUDIO_CONFIG_5 0x60 96 I_AUDIO_CONFIG_6 0x61 97 I_AUDIO_CONFIG_7 0x62 98 I_AUDIO_CONFIG_8 0x63 99 I_AUDIO_CONFIG_9 0x64 100 I_AUDIO_CONFIG_10 0x65 101 I_AUDIO_CONFIG_11 0x59 89 POL_REQ 0x5A 90 INPUT_CONF 0x5B 91 I_AUDIO_CONFIG_1 ...

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... CD_SONG_INFO_C21 155 CD_SONG_INFO_C22 156 CD_SONG_INFO_C23 157 CD_SONG_INFO_C24 158 CD_SONG_INFO_C25 159 CD_SONG_INFO_C26 160 CD_SONG_INFO_C27 161 CD_SONG_INFO_C28 162 CD_SONG_INFO_C29 163 CD_SONG_INFO_C30 164 CD_SONG_INFO_C31 165 CD_SONG_INFO_C32 166 CD_SONG_TYPE_INFO STA016A Type When RO AEC RO AEC RO AEC RO AEC RO AEC RO AEC RO AEC RO AEC RO AEC RO AEC RO AEC RO AEC ...

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... STA016A Register function COMMAND 12/43 Hex Dec 0xA7 167 NB_OF_CUR_TRACK 0xA8 168 NB_OF_CUR_DIR 0xA9 169 CD_CUR_STATUS 0xAA 170 CD_TRACK_FORMAT 0xAB 171 CD_NB_OF_SUB_DIR 0xAC 172 CD_NB_OF_SUB_FILE 0xAD 173 DIRECTORY_LEVEL 0xAE 174 DIR_IDENTIFIER_B1 0xAF 175 DIR_IDENTIFIER_B2 0xB0 176 DIR_IDENTIFIER_B3 0xB1 177 DIR_IDENTIFIER_B4 0xB2 ...

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... RESERVED 0x75 117 MIX_MODE 0x76 118 MIX_DLA 0x77 119 MIX_DLB 0x78 120 MIX_DRA 0x79 121 MIX_DRB 0x7A 122 TONE_ON 0x7B 123 TONE_FCUTH 0x7C 124 TONE_FCUTL 0x7D 125 TONE_GAINH 0x7E 126 TONE_GAINL 0x7F 127 TONE_GAIN_ATTEN STA016A Name Type When EDF EDF EDF ...

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... STA016A 6 REGISTER DESCRIPTION 6.1 VERSION registers description 6.1.1 VERSION : Address : 0x00 (0) Type : RO - DWT Software Reset : 0x10 Hardware Reset : 0x10 Description : The VERSION register is Read-only and it is used to identify the IC on the application board. 6.1.2 IDENT : Address : 0x01 (1) Type : RO - DWT Software Reset : 0xAC ...

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... This register must contain a NDIV value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running 14.31818 MHz PLL_AUDIO_PEH_176 : PLL_AUDIO_NDIV_176 : STA016A 15/43 ...

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... STA016A 6.2.9 PLL_AUDIO_XDIV_176 : Address : 0xE4 (228) Type : RW - DEC Software Reset : 2 Description : This register must contain a XDIV value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running at 14 ...

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... Description : This register must contain a XDIV value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz 6.3.11 PLL_SYSTEM_MDIV_42_5 : Address : 0xEA (234) PLL_SYSTEM_NDIV_42_5 : STA016A 17/43 ...

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... STA016A Type : RW - DEC Software Reset : 10 Description : This register must contain a MDIV value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz 2 6.4 I Sout_CONFIGURATION registers description 6 ...

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... Polarity of GPSO_REQ : 0 : data are valid when GPSO_REQ is high 1 : data are valid when GPSO_REQ is low Reserved : to be set to 0. INPUT_CONF : STA016A b1 b0 CF1 CF0 b1 b0 19/43 ...

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... STA016A 6.6.2 I_AUDIO_CONFIG_1 CF7 CF6 CF5 CF4 CF3 Address : 0x5B (91) Type : RW - DEC Software Reset : 0 Description : If INPUT_CONF == 1, this register configure the I2Sin interface Table 16. . Bit Comment fields CF0 Relative synchro : 0 : synchro with first data bit 1 : synchro one bit before first data bit ...

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... Reserved : to be set to 1 Direction of LR clocks CD_LRCK & BS_LRCK : 0 : input 1 : output Polarity of LR clocks CD_LRCK & BS_LRCK : 0 : left sample corresponds to the low level phase of LRCK 1 : left sample corresponds to the high level phase of LRCK Reserved : to be set to 0 I_AUDIO_CONFIG_2 : STA016A b1 b0 CF8 21/43 ...

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... STA016A Table 20. . Bit Comment CF8 Relative synchro : 0 : synchro with first data bit 1 : synchro one bit before first data bit CF9 Data reception configuration : 0 : LSB first 1 : MSB first CF10 Arithmetic type of the reception : 0 : unsigned data 1 : signed data CF11 Bit to select the reference clock used to generate BCK if clocks are in output (CF2=1 & ...

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... This register manage the polarity of the data REQ signal DREQ of the BS input interface. If set to 0, data are requested when REQ = set to 1, data are requested when REQ = 1. DV2 DV1 DV0 6.8.2 b7 Address : 0x5A (90) Type : RW - DEC Software Reset : 0 Description : POL_REQ : INPUT_CONF : STA016A b1 b0 DV8 23/43 ...

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... STA016A If set to 1 enable the configurability of the BSB input interfaces in burst mode thanks to following register, else disable this configurability and take embedded default configuration. Note that this embedded default configuration can be retrieved by user thanks to following setting : – I_AUDIO_CONFIG1 = b00000000;// polarity choice 6 ...

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... Type : RO - AEC Software Reset : 0 TYPE_CD_EXT_REQ Signification application is in pause after EOT or EOD request for a sector begin of track reached ready to receive a new command dsp ready to run cd application stopped. time spent on track available request for root song information available MINUTE_REQ : SECOND_REQ : STA016A 25/43 ...

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... STA016A Description : This register specifies to the CD module the second location requested. 6.9.8 SECTOR_REQ : Address : 0x49 (73) Type : RO - AEC Software Reset : 0 Description : This register specifies to the CD module the sector lo- cation requested. 6.9.9 MINUTE_SPENT : Address : 0x4A (74) Type : RO - AEC Software Reset : 0 Description : This register specifies the number of minute spent from the beginning of the track ...

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... This register gives the status of the CD application. Table 27 Bit Mode 0 0: unknown format. 1: recognized format 1 reserved searching track. 1: track founded ID3 present. 1: ID3 missing error detected. 1: error detected application in pause application not in pause not playable playable music mode. 1: searching bytes mode STA016A 27/43 ...

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... STA016A 6.9.19 CD_TRACK_FORMAT : Address : 0xAA (170) Type : RO - AEC Software Reset : 0 Description : This register specifies the format of the played track considering the extension name. Only 1 bit can be set in the same time Table 28. : Bit UNKNOWN 1 : MP3 1 1: RESERVED 2 MPEG1 3 MPEG2 4 MPG 6.9.20 NB_OF_SUBDIR : ...

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... This will begin the boot of the chip, and so get it out of its idle state. 6.10.3 DEC_SEL : b7 Address : 0x55 (85) Type : RW - DEC Software Reset : 0 FORMAT 0: ID3 tag not checked 1: ID3 tag checked reference for counting sector in minute STA016A 29/43 ...

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... STA016A Description : This register select the decoding data flux according the mode written in following table Table 30. . Bit(7:0) 0 CD_MP3 1 CD_BYPASSA 2 RESERVED 3 BSB_MP3 4 RESERVED 5 RESERVED 6 RESERVED 7 BSA_BYPASSA 8 RESERVED 9 I2Sin_BYPASSA 10 SINE (test mode chip alive) 6.10.4 RUN : Address : 0x56 (86) Type : RW - DEC Software Reset : 0 Description : – ...

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... STATUS_FE : b7 Address : 0x6F (111) Type : RO - AEC Software Reset : 0 Description : This register give the status of the synchronization process according following table. Table 32 Value Level 0 Syncrho not started 1 Syncword found 2 Syncword search 3 Syncword hard to find STA016A 31/43 ...

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... STA016A 6.11.5 HEADER _n Address : 0xD4 (212) to 0xD9 (217) Type : RO - EDF Software Reset : 0 Description : This register give the nth byte of the header of the frame currently decoded 6.11.6 PCMCLK_INPUT : Address : 0xCB (203) Type : RW - DEC Software Reset : 0 Description : If set to 1, the PCMCLK pad is configure as input in order to receive an external reference clock ...

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... Software Reset : 0 Description : This register specifies the rigth attenuation (in dB) on left channel 6.14 TONE_CONFIGURATION registers description 6.14.1 TONE_ON: b7 Address : 0x7A(122) Type : RW - ABO Software Reset : 0 Description : This register enables/diseables (1/0) the tone control. 6.14.2 TONE_FCUTH : b7 Address : 0x7B(123) Type : RW - ABO Software Reset : STA016A 33/43 ...

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... STA016A Description : This register specifies the high cut frequency: fcut(in Hz)=(TONE_FCUTH+1)*50. 6.14.3 TONE_FCUTL : Address : 0x7C(124) Type : RW - ABO Software Reset : 10 Description : This register specifies the low cut frequency: fcut(in Hz) = (TONE_FCUTL+1)*10 6.14.4 TONE_GAINH : Address : 0x7D(125) Type : RW - ABO Software Reset : 12 Description : This register specifies the gain on high frequencies: 6 ...

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... This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 512*SF. Register PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 CRYCK in MHz CRYCK in MHz 10 14.31818 224 108 190 140 118 CRYCK in MHz CRYCK in MHz 10 14.31818 42 58 169 187 157 16 157 STA016A CRYCK in MHz 14.7456 CRYCK in MHz 14.7456 35/43 ...

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... STA016A Table 39. values to configure system PLL for SYSCK. This table give values to configure the system PLL according CRYCK so that to generate a SYSCK == 50MHz. or SYSCK == 42.5MHz. Register PLL_SYSTEM_PEL_50 PLL_SYSTEM_PEH_50 PLL_SYSTEM_NDIV_50 PLL_SYSTEM_XDIV_50 PLL_SYSTEM_MDIV_50 PLL_SYSTEM_PEL_42_5 PLL_SYSTEM_PEH_42_5 PLL_SYSTEM_NDIV_42_5 PLL_SYSTEM_XDIV_42_5 PLL_SYSTEM_MDIV_42_5 Table 40. index of the Sampling Frequency. Index ...

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... TTL Tristate Output Pad Buffer, 3V capable 4mA, with Slew Rate Control Pin numbers: 4, 18, 20, 21, 22, 25, 54, 56 7.2 TTL Schmitt Trigger Bidir Pad Buffer, 3V capable, 4mA, with Slew Rate Control Pin numbers D98AU904 IO INPUT PIN IO D98AU905 INPUT PIN MAX LOAD Z 100pF OUTPUT CAPACITANCE PIN TBD IO STA016A MAX LOAD 100pF 37/43 ...

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... CD_module write its command inside dedicated host registers (mainly H64 to H69), then it must signals the writ- ing of this command to mmdsp by sending the interrupt IT_CMD to the core of mmdsp. Note that IT_CMD is generated by cd_module threw a falling edge on the input line number 0 of the STA016A 38/43 ...

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... MMDSP write its request inside dedicated host registers (mainly H70 to H78 and H134 to H169), then it signals to cd_module that it must read a request by sending the interrupt IT_REQ. Note that IT_REQ interrupt is generated by mmdsp on the IRQB pin of STA016A. Note also that once it has finished to read the message, cd_module must always acknowledge it by reading H10 ...

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... STA016A Figure 8. Block diagram for answer to a sector request from dsp. Hxx: host register number xx 40/43 power on IT_REQ occured H70==18 read minute in H71 please check with rest of documentation read second in H72 read frame in H73 acknowledge acknowledge IT_REQ IT_REQ move the pick-up ...

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... TQFP64 ( 1.4mm) 0.0031 TQFP64 STA016A OUTLINE AND MECHANICAL DATA 0.08mm ccc Seating Plane C K 0051434 E 41/43 ...

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... STA016A Table 41. Revision History Date Revision July 2004 42/43 1 First Issue Description of Changes ...

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