Z8622912PSG Zilog, Z8622912PSG Datasheet - Page 23

• Manufacturer Part Number: Z8622912PSG
• Description: IC CCD W/2ND I2C ADD 18-DIP
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8622912PSG

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: Z8622x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: CGROM
• Program Memory Size: 3.7 B
• Maximum Clock Frequency: 12 MHz
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Details

ZiLOG
A write command to the Z86229 should always be preceded
by executing a Status read to verify that the Z86229 is not
busy. The Status register data is output immediately fol-
lowing the reception of the Slave Address Read. If the RDY
bit is set, the master device can initiate its write sequence,
always beginning with the Start condition. The first byte of
a two-byte command is always written first.
An example of the master’s sequence for writing a two-byte
command (after RDY had been checked) would be:
Start
Slave Address Write/Slave ACK
CMD (master)/ Slave ACK
DATA (master)/Slave ACK
Stop
Reading Data Using the I
With the exception of the Serial Status (SS) register, which
may be read at any time, each read operation must be set
up before the data can be read from the serial output registers
of the Z86229. Data is set up for a read operation either au-
tomatically or manually. The XDS data reads are set up au-
tomatically upon recovery by setting a valid XDS FILTER
register selection. All other data read operations must be set
up manually using the READ SELECT commands RDS1
and RDS2. These commands load the selected data byte or
pair of bytes into the serial output register(s), setting the SS
register RD2 bit according to the number of data bytes re-
quested. The SS register DAV bit is also set at that time to
indicate the availability of data.
The Z86229 I
read sequences. All read sequences output the SS register
as the first output byte. If the serial status DAV bit is set, a
two or three byte read sequence can then be initiated, be-
ginning with a new STRT condition.
I 2 C One-Byte Write (Command)
Note:
the STRT condition of either WRITE sequence above. See the One-
Byte Read (Status Only) in Figure 10 for more information on reading
the Status Register.
I 2 CTwo-Byte Write (Command & Data)
A Status Register RDY bit must be read and checked prior to
STRT
STRT
Figure 9. I
2
C Bus supports one-, two-, and three-byte
(WRITE=28h)
(WRITE=28h)
SLAVE
ADDR
SLAVE
ADDR
2
C Bus WRITE (Command)
WRITE
WRITE
CMD
CMD
2
C Bus
STOP
WRITE
DATA
STOP
Caution:
The number of data bytes available is indicated by the state
of the RD2 bit of the serial status. In a typical read operation,
the status byte is read, and the DAV and RD2 bits are ex-
amined. If one or two data bytes are available, the data is
read in sequence, separated by acknowledges.
Note:
The slave’s sequence for reading two
three bytes including SSB) from the Z86229 is given as:
I 2 C One-Byte Read (Status Only)
Note: In all I
from the Z86229 must be acknowledged by the master with a
NACK (Not ACKnowledge).
I 2 C Two-Byte Read (Status & Data1)
I 2 C Three-Byte Read (Status, Data1, & Data2)
Start
Slave Address Read/Slave ACK
SS Byte/Master ACK
Byte (slave)/Master ACK
Byte (slave)/Master NACK
Stop
In all I
fined in Figure 10) the most recent byte read from the
Z86229 should be acknowledged by the master with a
NACK (Not ACKnowledge). It is also necessary to read
all available data in a read operation to clear the DAV bit
and permit subsequent reads. The DAV is cleared by the
master clocking out of the eighth bit of the most recent
data-byte read. The DAV is never cleared by just reading
the SSB (one-byte read) alone. All data is first output as
MSB.
If the DAV bit is not set, the I
STRT
not attempt to read any data bytes. Attempting to read
data bytes from the I
of data from the Z86229 output registers.
Figure 10. I
STRT
STRT
2
2
C Read operations (one, two, and three byte as de-
C Read operations defined herein, the last byte read
(READ=29h)
SLAVE
ADDR
(READ=29h)
(READ=29h)
SLAVE
SLAVE
ADDR
ADDR
2
C Bus READ (Command)
STATUS
SERIAL
(SSB)
2
C master device may cause a loss
STATUS
STATUS
SERIAL
SERIAL
(SSB)
(SSB)
READ
DATA1
2
C master device should
STOP
NACK
data bytes
NACK
DATA1
READ
READ
DATA2
STOP
NACK
(total of
STOP