Z8623012PSG Zilog, Z8623012PSG Datasheet - Page 22

• Manufacturer Part Number: Z8623012PSG
• Description: IC SMART V-CHIP W/2ND I2C 18-DIP
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8623012PSG

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: Z8623x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: CMOS
• Maximum Clock Frequency: 12 MHz
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Details

4.1.7 STOP Condition
4.1.8 Acknowledge
22
S
ERIAL
C
A Low-to-High transition of
minates all communications.
All address and data words are serially transmitted to and from the Z86230 in
eight bit words. A ninth bit time is used for the Acknowledge. The acknowledging
device pulls the
is returned by
F
T
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
OMMUNICATIONS
SCLK
LOW
High
R
F
AA
BUF
HD.STA
SU.STA
HD.DAT
SU.DAT
SU.STO
DH
I
IGURE
ABLE
SDA (OUT)
SDA (IN)
SCLK
6. I
6. I
t
SU.STA
2
2
t
Parameter
Clock Frequency
Clock Pulse Width Low
Clock Pulse Width High
SDA and SCL Rise Time
SDA and SCL Fall Time
Clock Low to Data Out Valid
Bus Free Time
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Stop Set-up Time
Data Out Hold Time
Input Filter Time Constant
C S
HD.STA
C S
SDA = High
ERIAL
ERIAL
Z86230—PRELIMINARY
SDA
I
NTERFACE
t
AA
t
F
T
bus Low during the ninth bit. A Not Acknowledge (
T
IMING
IMING
during the ninth clock time.
SDA
M
t
HD.DAT
IN
t
High
/M
t
with
DH
AX
SCLK
t
Low
t
High is a
SU.DAT
Min
250
100
4.7
4.0
0.1
4.7
4.0
4.7
4.7
0
–
–
STOP
t
R
PS000401-TVC0699
condition which ter-
Max
100
300
100
1.0
3.5
I
2
–
–
–
–
–
–
–
–
–
C B
t
t
BUF
SU.STO
US
O
NACK
PERATION
Units
kHz
ms
ms
ms
ms
ms
ms
ms
ms
ms
ns
ns
ns
ns
)