CS493105-CLZR Cirrus Logic Inc, CS493105-CLZR Datasheet - Page 43

• Manufacturer Part Number: CS493105-CLZR
• Description: IC DECODER AUD MULTI STD 44-PLCC
• Manufacturer: Cirrus Logic Inc
• Type: Audio Decoderr

Specifications of CS493105-CLZR

• Package / Case: 44-PLCC
• Applications: MP3 Players, Portable Media Players
• Voltage - Supply, Analog: 2.37 V ~ 2.63 V
• Voltage - Supply, Digital: 2.37 V ~ 2.63 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In
CS493XX, INTREQ will not go low unless the host
first sends a read request command message. In
other words the host must solicit a response from
the DSP. In this environment, the host must read
from the CS493XX until INTREQ goes high again.
Once the INTREQ pin has gone high it will not be
driven low until the host sends another read
request.
When unsolicited messages, such as those used
for Autodetect, have been enabled, the behavior of
INTREQ is noticeably different. The CS493XX will
drop the INTREQ pin whenever the DSP has an
outgoing message, even though the host may not
have requested data.
There are three ways in which INTREQ can be
affected by an unsolicited message:
1) During normal operation, while INTREQ is high,
the DSP could drop INTREQ to indicate an
outgoing message, without a prior read request.
2) The host is in the process of reading from the
CS493XX, meaning that INTREQ is already low.
An unsolicited message arrives which forces
INTREQ to remain low after the solicited message
is read.
3) The host is reading from the CS493XX when the
unsolicited message is queued, but INTREQ goes
high for one period of SCCLK and then goes low
again before the end of the read cycle.
In case (1) the host should perform a read
operation as discussed in the previous sections.
In case (2) an unsolicited message arrives before
the second to last SCCLK of the final byte transfer
of a read, forcing the INTREQ pin to remain low. In
this scenario the host should continue to read from
the CS493XX without a stop/start condition or data
will be lost.
In case (3) an unsolicited message arrives
between the second to last SCCLK and the last
SCCLK of the final byte transfer of a read. In this
scenario, INTREQ will transition high for one clock
(as if the read transaction has ended), and then
back low (indicating that more data has queued).
This final case is the most complicated and shall
be explained in detail.
DS339F7
general,
when
communicating
with
the
There are two constraints which completely
characterize the behavior of the INTREQ pin
during a read. The first constraint is that the
INTREQ pin is guaranteed to remain low until the
second to last SCCLK (SCCLK number N-1) of the
final byte being transferred from the CS493XX (not
necessarily the second to last bit of the data byte).
The second constraint is that once the INTREQ pin
has gone high it is guaranteed to remain high until
the rising edge of the last SCCLK (SCCLK number
N) of the final byte being transferred from the
CS493XX (not necessarily the last bit of the data
byte). If an unsolicited message arrives in the
window of time between the rising edge of the
second to last SCCLK and the final SCCLK,
INTREQ will drop low on the rising edge of the final
SCCLK as illustrated in the functional timing
diagrams shown for I
INTREQ behavior for I
illustrated in
When using I
will remain low until the rising edge of SCCLK for
the data bit D0 (SCCLK N-1), but it can go low at
the rising edge of SCCLK for the NACK bit (SCCLK
N) if an unsolicited message has arrived. If no
unsolicited messages arrive, the INTREQ pin will
remain high after rising.
INTREQ behavior for SPI communication is
illustrated in
When using SPI communication, the INTREQ pin
will remain low until the rising edge of SCCLK for
the data bit D1 (SCCLK N-1), but it can go low at
the rising edge of SCCLK for data bit D0 (SCCLK
N) if an unsolicited message has arrived. If no
unsolicited messages arrive, the INTREQ pin will
remain high after rising.
Ideally, the host will sample INTREQ on the falling
edge of SCCLK number N-1 of the final byte of
each read response message. If INTREQ is
sampled high, the host should conclude the current
read cycle using the stop condition defined for the
communication mode chosen. The host should
then begin a new read cycle complete with the
appropriate start condition and the chip address. If
INTREQ is sampled low, the host should continue
reading the next message from the CS493XX
without ending the current read cycle.
Figure 24, "I2C® Timing" on page
Figure 21, "SPI Timing" on page
2
C
®
CS49300 Family DSP
communication the INTREQ pin
2
C
®
and SPI read cycles.
2
C
®
communication is
42.
39.
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