AD1896AYRSZ Analog Devices Inc, AD1896AYRSZ Datasheet
AD1896AYRSZ
Specifications of AD1896AYRSZ
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AD1896AYRSZ Summary of contents
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FEATURES Automatically Senses Sample Frequencies No Programming Required Attenuates Sample Clock Jitter 3.3 V–5 V Input and 3.3 V Core Supply Voltages Accepts 16-/18-/20-/24-Bit Data Up to 192 kHz Sample Rate Input/Output Sample Ratios from 7.75:1 to 1:8 Bypass ...
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AD1896–SPECIFICATIONS TEST CONDITIONS, UNLESS OTHERWISE NOTED. Supply Voltages VDD_CORE VDD_IO Ambient Temperature Input Clock Input Signal Measurement Bandwidth Word Width Load Capacitance Input Voltage High Input Voltage Low Specifications subject to change without notice. DIGITAL PERFORMANCE (VDD_CORE = 3.3 V ...
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DIGITAL TIMING (–40 C < T < +105 C, VDD_CORE = 3 Parameter t MCLK_I Period MCLKI f MCLK_I Frequency MCLK t MCLK_I Pulsewidth High MPWH t MCLK_I Pulsewidth Low MPWL Input Serial Port Timing t LRCLK_I ...
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AD1896 TIMING DIAGRAMS LRCLK_I t LRIS SCLK I t DIS SDATA I t DIH LRCLK O SCLK O t DOPD SDATA O t LROS LRCLK O t LROH SCLK O t TDMS TDM IN t TDMH Figure 1. Input and ...
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DIGITAL FILTERS (VDD_CORE = 3.3 V Parameter Pass-Band Pass-Band Ripple Transition Band Stop-Band Stop-Band Attenuation Group Delay Specifications subject to change without notice. DIGITAL I/O CHARACTERISTICS (VDD_CORE = 3.3 V Parameter Input Voltage High ( Input Voltage Low ...
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AD1896 POWER SUPPLIES (VDD_CORE = 3.3 V Parameter Total Active Power Dissipation 48 kHz:48 kHz 96 kHz:96 kHz 192 kHz:192 kHz Total Power-Down Dissipation: (RESET LO) Specifications subject to change without notice. TEMPERATURE RANGE Parameter Specifications Guaranteed Functionality Guaranteed Storage ...
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Pin No. IN/OUT Mnemonic 1 IN GRPDLYS 2 IN MCLK_IN 3 OUT MCLK_OUT 4 IN SDATA_I 5 IN/OUT SCLK_I 6 IN/OUT LRCLK_I 7 IN VDD_IO 8 IN DGND 9 IN BYPASS 10 IN SMODE_IN_0 11 IN SMODE_IN_1 12 IN SMODE_IN_2 ...
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AD1896–Typical Performance Characteristics 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 2.5 5.0 7.5 10.0 12.5 FREQUENCY – kHz TPC 1. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:48 kHz (Asynchronous) 0 –20 ...
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FREQUENCY – kHz TPC 7. Wideband FFT Plot (16k Points) 192 kHz:48 kHz, 0 dBFS 1 kHz Tone –50 –60 –70 –80 –90 –100 ...
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AD1896 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 –190 –200 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY – kHz TPC 13. Wideband FFT Plot (16k Points) 96 kHz:48 kHz, –60 dBFS 1 kHz ...
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FREQUENCY – kHz TPC 19. Wideband FFT Plot (16k Points) 192 kHz:192 kHz, 0 dBFS 80 kHz Tone 0 –20 –40 –60 –80 –100 ...
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AD1896 –119 –121 –123 –125 –127 –129 –131 –133 –135 105 OUTPUT SAMPLE RATE – kHz TPC 25. THD + N vs. Output Sample Rate dBFS 1 kHz Tone –119 –121 –123 –125 –127 –129 ...
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OUTPUT SAMPLE RATE – kHz TPC 31. DNR vs. Output Sample Rate, f –60 dBFS 1 kHz Tone 0 –20 –40 192kHz:96kHz –60 192kHz:48kHz ...
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AD1896 –1 –2 –3 –4 –5 – – – – – 140 120 100 80 60 INPUT LEVEL – dBFS TPC 37. Linearity Error, 48 kHz:44.1 kHz, 0 dBFS to –140 dBFS Input, 200 ...
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INPUT LEVEL – dBFS TPC 43. THD + N vs. Input Amplitude, 48 kHz:44.1 kHz, 1 kHz Tone –110 –115 ...
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AD1896 –110 –115 –120 –125 –130 –135 –140 –145 –150 –155 –160 –165 –170 –175 –180 2.5 5.0 7.5 10.0 12.5 FREQUENCY – kHz TPC 49. THD + N vs. Frequency Input, 48 kHz:44.1 kHz, 0 dBFS –110 –115 –120 ...
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Page 1) The digital servo loop measures the time difference between the input and output sample rates within 5 ps. This is necessary in order to select the correct polyphase filter coefficient. The digital servo loop has excellent ...
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AD1896 ASRC FUNCTIONAL OVERVIEW THEORY OF OPERATION Asynchronous sample rate conversion is converting data from one clock source at some sample rate to another clock source at the same or a different sample rate. The simplest approach to an asynchronous ...
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IN INTERPOLATE LOW-PASS BY N FILTER f S_IN FREQUENCY DOMAIN OF SAMPLES AT f S_IN FREQUENCY DOMAIN OF THE INTERPOLATION SIN(X)/X OF ZERO-ORDER HOLD FREQUENCY DOMAIN OF f RESAMPLING S_OUT FREQUENCY DOMAIN AFTER RESAMPLING Figure 6. Frequency Domain of the ...
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AD1896 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 –190 –200 –210 –220 0.01 0.1 Figure 8. Frequency Response of the Digital Servo Loop. f Frequency Is 30 ...
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However, the hysteresis of the f /f S_OUT S_IN phase mismatching between two AD1896s operating with the same input clock and the same output clock. Since the hyster- esis requires a difference of more than two ratio ...
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AD1896 AD1896 MCLK_I C1 Figure 9a. Fundamental-Mode Circuit Configuration AD1896 MCLK_I C1 Figure 9b. Third-Overtone Circuit Configuration There are, of course, maximum and minimum operating fre- quencies for the AD1896 master clock. The maximum master clock frequency at which the ...
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LRCLK SCLK MSB MSB SDATA LRCLK SCLK MSB SDATA LRCLK SCLK MSB SDATA LRCLK SCLK MSB SDATA NOTES 1 LRCLK NORMALLY OPERATES AT ASSOCIATIVE INPUT OR OUTPUT SAMPLE FREQUENCY (f 2 SCLK FREQUENCY IS NORMALLY 64 WHERE N = NUMBER ...
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AD1896 AD1896 TDM_IN SDATA_O LRCLK_O SCLK_O CLOCK-MASTER AND PHASE-MASTER Figure 12. Daisy-Chain Configuration for TDM Mode (First AD1896 Being Clock-Master) MATCHED-PHASE MODE (NON-TDM MODE) APPLICATION LRCLK ( S_IN SCLK I AD1896 PHASE-MASTER ...
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Matched-Phase Mode The matched-phase mode is the mode discussed in the Theory of Operation section that eliminates the phase mismatch between multiple AD1896s. The master AD1896 device transmits its f /f ratio through the SDATA_O pin to the slave S_OUT ...
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AD1896 2.00 MAX 0.05 MIN OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9. 5.60 8.20 7.80 5.30 5.00 7. 1.85 1.75 0.10 COPLANARITY 1.65 0.25 0.09 0.38 0.65 ...
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Revision History Location 3/03—Data Sheet changed from REV REV. A. Edits to DIGITAL PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . ...
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