AD1895AYRSZ Analog Devices Inc, AD1895AYRSZ Datasheet - Page 21

• Manufacturer Part Number: AD1895AYRSZ
• Description: IC CONV SAMPLE RATE ASYNC 28SSOP
• Manufacturer: Analog Devices Inc
• Type: Sample Rate Converterr

Specifications of AD1895AYRSZ

• Applications: Automotive Audio, receivers, set-top boxes
• Voltage - Supply, Digital: 3.13 V ~ 3.46 V
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Audio Codec Type: Stereo
• No. Of Input Channels: 3
• No. Of Output Channels: 4
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 128dB
• Sampling Rate: 215kSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD1895EB - BOARD EVAL FOR AD1895
• Voltage - Supply, Analog: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TDM MODE APPLICATION
In TDM Mode, several AD1895s can be daisy-chained together
and connected to the serial input port of a SHARC
AD1895 contains a 64-bit parallel load shift register. When the
LRCLK_O pulse arrives, each AD1895 parallel loads its left and
right data into the 64-bit shift register. The input to the shift
register is connected to TDM_IN, while the output is connected
to SDATA_O. By connecting the SDATA_O to the TDM_IN
SHARC is a registered trademark of Analog Devices, Inc.
REV. B
LRCLK
SCLK
TDM_IN
TDM_IN
M2
M2
0
CLOCK-MASTER
0
AD1895
AD1895
Figure 12. Daisy-Chain Configuration for TDM Mode (First AD1895 Being Clock-Master)
SLAVE-1
Figure 11. Daisy-Chain Configuration for TDM Mode (All AD1895s Being Clock-Slaves)
M1
M1
0
1
LRCLK_O
LRCLK_O
SDATA_O
SDATA_O
SCLK_O
SCLK_O
M0
M0
0
1
TDM_IN
TDM_IN
M2
M2
0
0
AD1895
AD1895
SLAVE-2
SLAVE-1
®
M1
M1
0
0
DSP. The
LRCLK_O
LRCLK_O
SDATA_O
SDATA_O
SCLK_O
SCLK_O
M0
M0
0
0
–21–
of the next AD1895, a large shift register is created and is
clocked by SCLK_O.
The number of AD1895s that can be daisy-chained together is
limited by the maximum frequency of SCLK_O, which is about
25 MHz. For example, if the output sample rate, f
up to eight AD1895s could be connected since 512 × f
than 25 MHz. In Master/TDM Mode, the number of AD1895s
that can be daisy-chained is fixed to four.
TDM_IN
TDM_IN
M2
M2
0
0
AD1895
AD1895
SLAVE-n
SLAVE-n
M1
M1
0
0
LRCLK_O
LRCLK_O
SDATA_O
SDATA_O
SCLK_O
SCLK_O
M0
M0
0
0
STANDARD MODE
STANDARD MODE
DR0
RFS0
RCLK0
DR0
RFS0
RCLK0
SHARC
SHARC
DSP
DSP
AD1895
S
, is 48 kHz,
S
is less