MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 431

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

Write: Anytime for output compare function.Writes to these registers have no meaning or effect during
input capture. All timer input capture/output compare registers are reset to 0x0000.
13.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)
When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7.
Read: Any time
Write: Any time
Freescale Semiconductor
CLK[1:0]
PAMOD
PEDGE
Reset
PAEN
Field
3:2
6
5
4
W
R
Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator system disabled.
1 Pulse Accumulator system enabled.
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See
Table
0 Event counter mode.
1 Gated time accumulation mode.
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode). See
0 Falling edges on IOC7 pin cause the count to be incremented.
1 Rising edges on IOC7 pin cause the count to be incremented.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
Clock Select Bits — Refer to
0
0
7
edge on IOC7 sets the PAIF flag.
on IOC7 sets the PAIF flag.
Read/Write access in byte mode for high byte should takes place before low
byte otherwise it will give a different result.
13-18.
Figure 13-22. 16-Bit Pulse Accumulator Control Register (PACTL)
Unimplemented or Reserved
PAEN
0
6
Table 13-17. PACTL Field Descriptions
PAMOD
MC9S12E128 Data Sheet, Rev. 1.07
Table
0
5
13-19.
PEDGE
NOTE
0
4
Table
Description
13-18.
CLK1
0
3
CLK0
Chapter 13 Timer Module (TIM16B4CV1)
0
2
PAOVI
0
1
PAI
0
0
431