MAX3746ETE Maxim Integrated Products, MAX3746ETE Datasheet - Page 8

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MAX3746ETE

Manufacturer Part Number
MAX3746ETE
Description
Limiting Amplifiers 622Mbps to 3.2Gbps
Manufacturer
Maxim Integrated Products
Datasheets

Specifications of MAX3746ETE

Operating Supply Voltage
3.3 V
Supply Current
35 mA
Operating Temperature Range
+ 85 C
Package / Case
TQFN EP
Mounting Style
SMD/SMT
Number Of Channels
1
Power Dissipation
1400 mW
Lead Free Status / Rohs Status
No
The MAX3746 is equipped with multirate LOS circuitry
that indicates when the input signal is below a pro-
grammable threshold, set by resistor R
(see the Typical Operating Characteristics for appropri-
ate resistor sizing). An averaging RMS power detector
compares the input signal amplitude with this threshold
and feeds the signal-detect information to the open-col-
lector LOS output.
To prevent LOS chatter in the region of the pro-
grammed threshold, approximately 2dB of hysteresis is
Low-Power, 622Mbps to 3.2Gbps
Limiting Amplifier
Figure 1. Power-Supply Current Measurement
Figure 3. CML Input Buffer
8
Power Detect and Loss-of-Signal Indicator
IN+
IN-
0.25pF
0.25pF
_______________________________________________________________________________________
STRUCTURES
ESD
V
CC
MAX3746
I
CC
(SUPPLY CURRENT)
50Ω
50Ω
50Ω
V
CC
R
TH
50Ω
TH
I
OUTPUT CURRENT)
OUT
at the TH pin
(CML
built into the LOS assert/deassert function. Once
asserted, the LOS is not deasserted until the input
amplitude rises to the required level (V
Figures 2 and 5.)
External resistor, R
threshold. See the LOS Threshold vs. R
Typical Operating Characteristics to select the appro-
priate resistor.
Figure 2. LOS Assert Threshold Set 1dB Below the Minimum by
Receiver Sensitivity for Selected R
Figure 4. CML Output Buffer
I1 = f (OUTPOL, DISABLE)
0V
DISABLE
DATA
V
IN
1dB
6dB
Program the LOS Assert Threshold
Q3
POWER-DETECT WINDOW
MAX DEASSERT LEVEL
Q4
MIN ASSERT LEVEL
I2 = f (OUTPOL, DISABLE)
SIGNAL OFF
SIGNAL ON
TH,
programs the loss-of-signal
50Ω
Design Procedure
Q1
TH
V
CC
Q2
50Ω
DEASSERT
TH
graph in the
TIME
STRUCTURES
). (See
ESD
OUT+
OUT-

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