DS2181AQ Maxim Integrated Products, DS2181AQ Datasheet - Page 20

IC TXRX CEPT PRIMARY RATE 44PLCC

DS2181AQ

Manufacturer Part Number
DS2181AQ
Description
IC TXRX CEPT PRIMARY RATE 44PLCC
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet

Specifications of DS2181AQ

Number Of Drivers/receivers
1/1
Protocol
CEPT
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
44-LCC, 44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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RSR: RECEIVE STATUS REGISTER Figure 18
(MSB)
NOTE:
1. When in the CCS mode, the RDMA flag bit and the RDMA pin have no significance. It will be set
SYMBOL
MFSERR
when bit 6 of timeslot 16 in frame 0 is set for three consecutive multiframes in either CAS or CCS
mode.
RDMA
FSERR
RUA1
RLOS
RRA
RSA1
RRA
ECS
RDMA
POSITION
RSR.7
RSR.6
RSR.5
RSR.4
RSR.3
RSR.2
RSR.1
RSR.0
RSA1
NAME AND DESCRIPTION
Receive Remote Alarm. Set when bit 3 of timeslot 0 in non-align
frames set for three consecutive non-align frames.
Receive Distant Multiframe Alarm. Set when bit 6 of timeslot 16
in frame 0 is set for three consecutive multiframes.
Receive Signaling All Ones. Set when the contents of timeslot 16
have been all 1's for two consecutive frames.
Receive Unframed All Ones. Set when less than three 0s have
been received in the last two consecutive frames.
Frame Resync Criteria Met. Set when the frame error criteria are
met; also the frame resync is initiated if RCR.1=0.
CAS Multiframe Resync Criteria Met. Set when the CAS
multiframe error criteria are met; also, the frame resync is initiated
if RCR.1=0.
Receive Loss of Sync. Set when resync is in progress.
Error Counter Saturation. Set when any of the on-chip counters
at FECR, CECR or BVCR saturates.
RUA1
20 of 32
FSERR
MFSERR
RLOS
(LSB)
DS2181A
ECS

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