IS43DR16160A-37CBL ISSI, Integrated Silicon Solution Inc, IS43DR16160A-37CBL Datasheet - Page 22

no-image

IS43DR16160A-37CBL

Manufacturer Part Number
IS43DR16160A-37CBL
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
DDR2 SDRAMr
Datasheet

Specifications of IS43DR16160A-37CBL

Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
500ps
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Package Type
WBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
270mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS43DR16160A-37CBL
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS43DR16160A-37CBL
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS43DR16160A-37CBL-TR
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS43DR16160A-37CBLI
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS43DR16160A-37CBLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS43DR16160A-37CBLI
Manufacturer:
ISSI
Quantity:
20 000
IS43/46DR83200A, IS43/46DR16160A
Data Input (Write) Timing
Data Output (Read) Timing
5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions.
6. All voltages are referenced to VSS.
7. These parameters guarantee device behavior, but they are not necessarily tested on each device They may be
guaranteed by device design or tester correlation.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
Specific Notes for Dedicated AC Parameters
1. User can choose which active power down exit timing to use via Mode Register Set [A12]. tXARD is expected to be
used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing.
2. AL = Additive Latency.
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and
tRAS(min) have been satisfied.
4. A minimum of two clocks (2 x tCK or 2 x nCK) is required irrespective of operating frequency.
5. Timings are specified with command/address input slew rate of 1.0 V/ns. See Specific Notes on derating for other
slew rate values.
6. Timings are specified with DQs, DM, and DQS’s (DQS/RDQS in single ended mode) input slew rate of 1.0V/ns. See
Specific Notes on derating for other slew rate values.
22
CK/CK
DQS/DQS
DQ
DQS/
DQS
DQ
DM
CK
CK
t
DQS
DQS
WPRE
DQS
DQS
t
V
V
CH
IH
IL
(ac)
(ac)
t
DMin
DS
D
t
RPRE
t
DQSH
V
V
t
t
IH
IL
CL
DQSQmax
(ac)
(ac)
t
DMin
DS
D
t
DQSL
t
QH
Q
DMin
D
t
DH
V
V
IH
IL
(dc)
(dc)
Q
DMin
D
t
DH
V
V
IH
IL
t
(dc)
WPST
(dc)
t
DQSQmax
Integrated Silicon Solution, Inc. — www.issi.com
Q
t
t
RPST
QH
Q
12/16/2010
Rev.  00D

Related parts for IS43DR16160A-37CBL