CLC012AJE National Semiconductor, CLC012AJE Datasheet - Page 10

• Manufacturer Part Number: CLC012AJE
• Manufacturer: National Semiconductor

Specifications of CLC012AJE

• Lead Free Status / Rohs Status: Not Compliant

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Output Interfacing
DIFFERENTIAL SOURCE-TERMINATED OUTPUT
INTERFACE
Figure 6 is similar to Figure 5 except that the termination is
provided at the source. This configuration may also be used
for single-ended applications. However, the unused output
must still be terminated as shown.
TERMINATING PHYSICALLY SEPARATED OUTPUTS
When the two outputs must be routed to physically separate
locations, the circuit in Figure 6 may be applied. Alterna-
tively, if load termination is desired, the circuit in Figure 7
may be used. The resistive divider network provides 75Ω
termination and establishes proper ECL levels. This circuit
consumes slightly more power than the previous circuits.
FIGURE 6. Differential Source Terminated
FIGURE 7. Alternative Load Terminated
Output Interface
Output Interface
(Continued)
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10
Design Guidelines
SELECTING THE AUTOMATIC EQUALIZER CAPACITOR
The AEC capacitor sets the loop time constant τ for the
equalizer’s adaptive loop response time. The following for-
mula is used to set the loop time constant:
R is a conversion factor that is set by internal equalizer
parameters and cable length. For Belden 8281 coaxial
cable, the R values are (τ = µs, C
For example, a C
loop time constant of 2 µs at 200 meters of cable.
CONNECTION AND OPERATION OF LOS AND MUTE
Loss of Signal (LOS) is a CMOS output that indicates the
presence of equalized data from the filter. This LOS output
can be connected to MUTE to suspend changes in the data
outputs DO and DO, if no valid signal exists. This simple
configuration prevents random output transitions due to
noise. For sparse transition patterns it is recommended that
a capacitor be connected to LOS as shown in Figure 1.
Add a capacitor to pin 5 to slow the response time of Loss of
Signal when LOS is connected to MUTE. The capacitor
reduces sensitivity to pathological patterns. Pathological pat-
terns are defined as sparse data sequences with few transi-
tions.
OUTPUT EYE MONITOR OEM CONNECTIONS
The OEM is a high-speed, buffered output for monitoring the
equalized eye pattern prior to the output comparator. Its
output is designed to drive an AC-coupled 50Ω coaxial cable
with a series 50Ω backmatch resistor. The cable should be
terminated with 50Ω at the oscilloscope. Figure 1 shows a
schematic with a typical connection.
MINIMUM DATA TRANSITIONS
The CLC012 specifies a minimum transition rate. For the
CLC012 this sets the minimum data rate for transmitting data
through any cable medium. The CLC012 minimum average
transition density is found in the Electrical Characteristics
section of the datasheet.
POWER SUPPLY OPERATION AND THERMAL
CONSIDERATIONS
The CLC012 operates from either +5V or −5.2V single sup-
plies. Refer to Figure 1 when operating the part from +5V.
When operating with a −5.2V supply, the V
bypassed to ground. The evaluation board and associated
literature provide for operation from either supply.
Maximum power dissipation occurs at minimum cable
length. Under that condition, I
Total power dissipated:
Power in the load:
Maximum power dissipated on the die:
P
P
T
L
= (0.7V)(11 mA) + (37.5)(11 mA)
= (58 mA)(5V) = 290 mW
100 meters
200 meters
300 meters
AEC
Length
τ = R • C
Cable
value of 100 pF results in an adaptive
AEC
CC
R Value
(Ohms)
= 58 mA.
• 10
15000
20000
32000
AEC
−6
2
in pF):
= 12 mW
EE
pins should be