PIC16C505-04I/P Microchip Technology Inc., PIC16C505-04I/P Datasheet - Page 17

• Manufacturer Part Number: PIC16C505-04I/P
• Description: 14 PIN, 1.5 KB OTP, 72 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C505-04I/P

• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 11
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 1.5K Bytes
• Ram Size: 72 Bytes
• Speed: 4 MHz
• Timers: 1- 8-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.6
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0>. Bit 5 of the STATUS register
provides page information to bit 9 of the PC
(Figure 4-3).
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-3).
Instructions where the PCL is the destination, or
Modify PCL instructions, include MOVWF PC, ADDWF
PC, and BSF PC,5.
FIGURE 4-3:
CALL or Modify PCL Instruction
GOTO Instruction
Note:
1999 Microchip Technology Inc.
PC
PC
Program Counter
11
11
Because PC<8> is cleared in the CALL
instruction or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any pro-
gram memory page (512 words long).
7
7
10
10
9
STATUS
9
STATUS
LOADING OF PC
BRANCH INSTRUCTIONS -
PIC16C505
PA0
Reset to ‘0’
PA0
8 7
8 7
Instruction Word
Instruction Word
PCL
PCL
0
0
0
0
4.6.1
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page (i.e., the oscillator calibration instruction.)
After executing MOVLW
location 00h and begin executing user code.
The STATUS register page preselect bits are cleared
upon a RESET, which means that page 0 is pre-
selected.
Therefore, upon a RESET, a
automatically cause the program to jump to page 0
until the value of the page bits is altered.
4.7
PIC16C505 devices have a 12-bit wide hardware
push/pop stack.
A CALL instruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
A RETLW instruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the
program memory.
Note 1: There are no STATUS bits to indicate
Note 2: There are no instructions mnemonics
EFFECTS OF RESET
Stack
stack overflows or stack underflow condi-
tions.
called PUSH or POP. These are actions that
occur from the execution of the CALL,
RETLW, and instructions.
XX, the PC will roll over to
PIC16C505
GOTO instruction will
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