IDT70V24S55PFG IDT, Integrated Device Technology Inc, IDT70V24S55PFG Datasheet - Page 14

• Manufacturer Part Number: IDT70V24S55PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70V24S55PFG

• Density: 64Kb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 24b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 180mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 16b
• Number Of Words: 4K
• Lead Free Status / Rohs Status: Compliant

NOTES:
1. R/W or CE or UB & LB must be HIGH during all address transitions.
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition the outputs remain in the HIGH-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W, or UB or LB.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
9. To access SRAM, CE = V
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
CE or SEM
CE or SEM
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing
ADDRESS
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
CE or SEM
ADDRESS
DATA
(Figure 2).
placed on the bus for the required t
the specified t
WR
UB or LB
DATA
DATA
is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle.
R/W
OUT
R/W
OE
IN
IN
(9)
(9)
(9)
(9)
WP
.
IL
,
UB or LB
t
AS
EW
DW
t
AS
=
(6)
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
or t
V
(6)
IL
,
WP
and SEM = V
(4)
) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
IH
t
.
WZ
To access Semaphore, CE = V
(7)
t
t
AW
AW
t
WC
t
WC
t
t
WP
EW
(2)
(2)
6.42
14
t
t
IH
DW
DW
or UB and LB
WP
or (t
Industrial and Commercial Temperature Ranges
t
WZ
WR
=
+ t
(3)
V
DW
IH
,
t
t
) to allow the I/O drivers to turn off and data to be
t
DH
and SEM = V
DH
WR
t
OW
(3)
IL
.
t
EW
t
HZ
must be met for either condition.
(7)
(4)
(1,5,8)
5624 drw 10
5624 drw 09
(1,5)