MAX696MJE/883B Maxim Integrated Products, MAX696MJE/883B Datasheet - Page 11

• Manufacturer Part Number: MAX696MJE/883B
• Description: Supervisory Circuits MPU Supervisor
• Manufacturer: Maxim Integrated Products

Specifications of MAX696MJE/883B

• Monitored Voltage: 3 V to 5.5 V
• Output Type: Active High, Active Low, Push-Pull
• Manual Reset: Not Resettable
• Watchdog: Watchdog
• Battery Backup Switching: Backup
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current (typ): 300 uA
• Maximum Power Dissipation: 600 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Package / Case: CDIP-16
• Minimum Operating Temperature: - 55 C
• Power Fail Detection: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 6. Watchdog Timer Block Diagram
becomes effective following the first transition of WDI
after RESET has gone high. The watchdog timer is
restarted at the end of reset, whether the reset was
caused by lack of activity on WDI or by LL
below 1.3V. If WDI remains either high or low, reset puls-
es will be issued every 1.6s. The watchdog monitor can
be deactivated by floating the watchdog input (WDI).
The watchdog output (WDO) goes low if the watchdog
timer times out, and it remains low until set high by the
next transition on the watchdog input. WDO is also set
high when LL
The watchdog timeout period defaults to 1.6s and the
reset pulse width defaults to 50ms. The MAX696 and
MAX697 allow these times to be adjusted per Table 1.
WATCHDOG INPUT
IN
V
goes below 1.3V.
CC
FOR EACH TRANSITION
______________________________________________________________________________________
(HI IF LL
1.0V
2.7V
LOW LINE
IN
+
-
+
-
< 1.3V)
TRANSITION
DETECTOR
Microprocessor Supervisory Circuits
INPUT IS FLOATING
HI IF WATCHDOG
IN
falling
S
R
RESET RESET
COUNTER
FLIP FLOP
Q
RESET
RESET
Q10/12
R
Q
The internal oscillator is enabled when OSC SEL is high
or floating. In this mode, OSC IN selects between the 1.6s
and 100ms watchdog timeout periods. In either case,
immediately after a reset, the timeout period is 1.6s. This
gives the microprocessor time to reinitialize the system.
WD transmissions while RESET is low are ignored. If OSC
IN is low, then the 100ms watchdog period becomes
effective after the first transition of WDI. The software
should be written so the I/O port driving WDI is left in its
power-up reset state until the initialization routines are
completed and the microprocessor is able to toggle WDI
at the minimum 70ms watchdog timeout period.
PRESCALER
Q6
R
S
LONG/SHORT
WATCHDOG
COUNTER
FF
R
OR EXTERNALLY SET FREQUENCY FROM
10.24kHz FROM INTERNAL OSCILLATOR
Q
Q11
Q13
Q15
LOW
LINE
OSC IN PIN
WATCHDOG TIMEOUT SELECT
WATCHDOG OUTPUT
WATCHDOG
WATCHDOG
SELECTOR
R
TIMEOUT
FAULT FF
LOGIC
Q
S
END OF WATCHDOG
GOES HIGH AT THE
TIMEOUT PERIOD
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