KSZ8721CL TR Micrel Inc, KSZ8721CL TR Datasheet

TXRX 10/100 3.3V 48-LQFP

KSZ8721CL TR

Manufacturer Part Number
KSZ8721CL TR
Description
TXRX 10/100 3.3V 48-LQFP
Manufacturer
Micrel Inc
Type
Transceiverr
Datasheet

Specifications of KSZ8721CL TR

Number Of Drivers/receivers
1/1
Protocol
MII
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
KSZ8721CLTR
KSZ8721CLTR
General Description
The KS8721CL is a 10BASE-T, 100BASE-TX, and 100BASE-
FX physical layer transceiver providing MII/RMII interfaces to
MACs and switches. Using a unique mixed-signal design that
extends signaling distance while reducing power consump-
tion, the KS8721CL represents Micrel’s fourth generation
single-port Fast Ethernet PHY.
The KS8721CL contains 10BASE-T physical medium attach-
ment (PMA), physical medium dependent (PMD), and physi-
cal coding sub-layer (PCS) functions. It also has on-chip
10BASE-T output filtering. This eliminates the need for
external filters and allows a single set of line magnetics to be
used to meet requirements for both 100BASE-TX and
10BASE-T.
The KS8721CL automatically configures itself for 100Mbps
or 10Mbps and full- or half-duplex operation, using an on-chip
auto-negotiation algorithm. It is the ideal physical layer
transceiver for 100BASE-TX/10BASE-T applications.
Functional Diagram
April 2005
KS8721CL
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
TX+
TX-
RX+
RX-
XO
XI
Transmitter
PLL
Wander Correction
10BaseT
Receiver
MLT3 Decoder
Adaptive EQ
NRZI/NRZ
Base Line
10/100
Shaper
Pulse
MLT3 Encoder
NRZ/NRZI
Negotiation
PWRDWN
Recovery
Down or
Saving
Power
Clock
Auto
1
Features
• Single chip 100BASE-TX/100BASE-FX/10BASE-T
• 2.5V CMOS design; 2.5/3.3V tolerance on I/O
• 3.3V single power supply with built-in voltage regulator;
• Fully compliant to IEEE 802.3u standard
• Supports MII and Reduced MII (RMII)
• Supports 10BASE-T, 100BASE-TX, and 100BASE-FX
• Supports power-down and power-saving modes
• Configurable through MII serial management ports or via
• Supports auto-negotiation and manual selection for
• On-chip, built-in, analog front-end filtering for both
• Available in Lead-free and Industrial Temperature
3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver
physical layer solution
Power consumption <340mW (including output driver
current)
with far-end-fault (FEF) detection
external control pins
10/100Mbps speed and full-/half-duplex modes
100BASE-TX and 10BASE-T
packages.
Manchester Encoder
Manchester Decoder
4B/5B Decoder
4B/5B Encoder
Parallel/Serial
Parallel/Serial
Serial/Parallel
Serial/Parallel
Descrambler
Scrambler
KS8721CL
Rev. 1.2
Registers
Controller
Interface
MII/RMII
Driver
LED
and
ACTIVITY
TXD3
TXD2
CRS
MDIO
MDC
RXD3
RXD2
SPD
TXD1
TXD0
TXER
TXC
TXEN
COL
RXD1
RXD0
RXER
RXDV
RXC
LINK
FDX
M9999-041405
Micrel, Inc.

Related parts for KSZ8721CL TR

KSZ8721CL TR Summary of contents

Page 1

KS8721CL General Description The KS8721CL is a 10BASE-T, 100BASE-TX, and 100BASE- FX physical layer transceiver providing MII/RMII interfaces to MACs and switches. Using a unique mixed-signal design that extends signaling distance while reducing power consump- tion, the KS8721CL represents Micrel’s ...

Page 2

KS8721CL Features (continued) • LED outputs for link, activity, full-/half-duplex, and speed • Supports back-to-back for media converter applications • Supports MDI/MDI-X auto-crossover • Commercial temperature range: 0°C to +70°C • Industrial temperature range: –40°C to +85°C ...

Page 3

KS8721CL Revision History Revision Date Summary of Changes 0.90 7/20/04 Created. 1.0 10/08/04 Updated series resistance for crystal specification to 40Ω. 1.1 1/27/05 MDIO resistor value changes to 4.7kΩ. Added note on strapping option pins. Updated bits 1b.0 - 1b.7 ...

Page 4

KS8721CL Table Of Contents Pin Description ............................................................................................................................................................ 6 Strapping Option ......................................................................................................................................................... 9 Pin Configuration ...................................................................................................................................................... 10 Introduction ........................................................................................................................................................... 11 100BASE-TX Transmit ........................................................................................................................................ 11 100BASE-TX Receive ......................................................................................................................................... 11 PLL Clock Synthesizer ......................................................................................................................................... 11 Scrambler/De-scrambler (100BASE-TX only) ..................................................................................................... 11 10BASE-T Transmit ............................................................................................................................................. ...

Page 5

KS8721CL Register Map (continued) Register 15h: RXER Counter ...................................................................................................................................... 21 Register 1bh: Interrupt Control/Status Register .......................................................................................................... 21 Register 1fh: 100BASE-TX PHY Controller ................................................................................................................ 21 Absolute Maximum Ratings ........................................................................................................................................ 23 Operating Ratings ........................................................................................................................................................ 23 Electrical Characteristics ............................................................................................................................................ 23 Timing Diagrams .......................................................................................................................................................... ...

Page 6

KS8721CL Pin Description Pin Number Pin Name Type 1 MDIO I/O 2 MDC I 3 RXD3/ Ipd/O PHYAD 4 RXD2/ Ipd/O PHYAD2 5 RXD1/ Ipd/O PHYAD3 6 RXD0/ Ipd/O PHYAD4 7 VDDIO P 8 GND GND 9 RXDV/ Ipd/O CRSDV/ ...

Page 7

KS8721CL Pin Number Pin Name Type 19 TXD2 Ipd 20 TXD3 Ipd 21 COL/RMII Ipd/O 22 CRS/ Ipd/O RMII_BTB 23 GND GND 24 VDDIO P 25 INT#/ Ipu/O PHYAD0 26 LED0/TEST Ipu/O PHYAD0 27 LED1/ Ipu/O SPD100/ nFEF 28 LED2/ ...

Page 8

KS8721CL Pin Number Pin Name Type 31 VDDRX 32 RX- 33 RX+ 34 FXSD/FXEN Ipd/O 35 GND GND 36 GND GND 37 REXT 38 VDDRCV 39 GND GND 40 TX- 41 TX+ 42 VDDTX 43 GND GND 44 GND GND ...

Page 9

KS8721CL (1) Strapping Options Pin Number Pin Name Type 6,5, PHYAD[4:1]/ Ipd/O 4,3 RXD[0:3] 25 PHYAD0/ Ipu/O INT# (3) 9 PCS_LPBK/ Ipd/O RXDV (3) 11 ISO/RXER Ipd/O (3) 21 RMII/COL Ipd/O (3) 22 RMII_BTB Ipd/O CRS 27 SPD100/ Ipu/O No ...

Page 10

KS8721CL Pin Configuration RXD3/PHYAD1 RXD2/PHYAD2 RXD1/PHYAD3 RXD0/PHYAD4 RXDV/PCS_LPBK M9999-041405 MDIO 1 MDC VDDIO 7 GND RXC RXER/ISO 11 GND 12 ...

Page 11

KS8721CL Introduction 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, NRZ-to-NRZI conversion, and MLT-3 encoding and transmission. The circuitry starts with a parallel to serial conversion that converts the 25MHz, 4-bit nibbles into a 125MHz serial bit stream. The ...

Page 12

KS8721CL auto-negotiation is enabled. It can also be configured to advertise 100BASE-TX or 10BASE-T in either full- or half-duplex mode (please refer to “Auto-Negotiation”). Auto-negotiation is disabled in the FX mode. During auto-negotiation, the contents of Register 4, coded in ...

Page 13

KS8721CL asserted. For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker. Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same ...

Page 14

KS8721CL to the RMII. TX_EN is negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN transitions synchronously with respect to REF_CLK. Transmit Data [1:0] (TXD[1:0]) Transmit Data TXD[1:0] transitions synchronously with respect to REF_CLK. When ...

Page 15

KS8721CL RMII Receive Timing REF_CLK RXD[1:0] RXDV RXER Parameter REF_CLK Frequency RXD[1:0], CRS_DV, RX_ER Output delay from REF_CLK rising edge Auto-Crossover (Auto-MDI/MDI-X) Automatic MDI/MDI-X configuration is intended to eliminate the need for crossover cables between similar devices. The assignment of ...

Page 16

KS8721CL Power Management The KS8721CL offers the following modes for power management: • Power-Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# low. • Power-Saving Mode: This mode can be disabled by ...

Page 17

KS8721CL Circuit Design Reference for Power Supply Micrel’s integrated built-in, voltage regulator technology allows the user to save BOM costs on both existing and future designs with the use of the new KS8721CL single supply, single port, 10/100 Ethernet PHY. ...

Page 18

KS8721CL Register Map Register No. Description 0h Basic Control Register 1h Basic Status Register 2h PHY Identifier I 3h PHY Identifier II 4h Auto-Negotiation Advertisement Register 5h Auto-Negotiation Link Partner Ability Register 6h Auto-Negotiation Expansion Register 7h Auto-Negotiation Next Page ...

Page 19

KS8721CL Address Name 1.10:7 Reserved 1.6 No Preamble 1.5 Auto-Negotiation Complete 1.4 Remote Fault 1.3 Auto-Negotiation Ability 1.2 Link Status 1.1 Jabber Detect 1.0 Extended Capability Register 2h - PHY Identifier 1 2.15:0 PHY ID Number Register 3h - PHY ...

Page 20

KS8721CL Address Name 5.11:10 Pause 5.9 100 BASE-T4 5.8 100BASE-TX Full-Duplex 5.7 100BASE-TX 5.6 10BASE-T Full-Duplex 5.5 10BASE-T 5.4:0 Selector Field Register 6h - Auto-Negotiation Expansion 6.15:5 Reserved 6.4 Parallel Detection Fault 6.3 Link Partner Next Page Able 6.2 Next ...

Page 21

KS8721CL Address Name Register 15h - RXER Counter 15.15:0 RXER Counter Register 1bh - Interrupt Control/Status Register 1b.15 Jabber Interrupt Enable 1b.14 Receive Error Interrupt Enable 1b.13 Page Received Interrupt Enable 1b.12 Parallel Detect Fault Interrupt Enable 1b.11 Link Partner ...

Page 22

KS8721CL Address Name 1f.6 Enable Pause (Flow-Control Result) 1f.5 PHY Isolate 1f.4:2 Reserved 1f.1 Enable SQE Test 1f.0 Disable Data Scrambling Note: 1. RW: Read/Write, RO: Read Only, SC: Self Clear, LH: Latch High, LL: Latch Low. Some of the ...

Page 23

KS8721CL Absolute Maximum Ratings Storage Temperature (T ) ....................... –55°C to +150°C S Supply Referenced to GND ........................ –0.5V to +4.0V All Pins ........................................................ –0.5V to +4.0V Important: Please read the Notes at the bottom of the page. Electrical Characteristics ...

Page 24

KS8721CL Symbol Parameter 100BASE-TX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot V Reference Voltage of ISET SET Propagation Delay Jitters 10BASE-TX Receive R RX+/RX– Differential IN Input Resistance V Squelch Threshold SQ 10BASE-TX Transmit (measured differentially after ...

Page 25

KS8721CL Timing Diagrams Symbol Parameter t TXD [3:0] Set-Up to TXC High SU1 t TXEN Set-Up to TXC High SU2 t TXD [3:0] Hold After TXC High HD1 t TXEN Hold After TXC High HD2 t TXEN High to CRS ...

Page 26

KS8721CL TXC TXEN TXD[3:0], TXER CRS TX+/TX- Symbol Parameter t TXD [3:0] Set-Up to TXC High SU1 t TXEN Set-Up to TXC High SU2 t TXD [3:0] Hold After TXC High HD1 t TXER Hold After TXC High HD2 t ...

Page 27

KS8721CL RX+/RX- CRS RXDV RXD[3:0] RXER RXC Symbol Parameter t RXC Period P t RXC Pulse Width WL t RXC Pulse Width WH t RXD [3:0], RXER, RXDV Set-Up to Rising Edge of RXC SU t RXD [3:0], RXER, RXDV ...

Page 28

KS8721CL TX+/TX- TX+/TX- Figure 8. Auto-Negotiation/Fast Link Pulse Timing Symbol Parameter t FLP Burst to FLP Burst BTB t FLP Burst Width FLPW t Clock/Data Pulse Width PW t Clock Pulse to Data Pulse CTD t Clock Pulse to Clock ...

Page 29

KS8721CL MDC MDI O (Into Ch ip) MDI O (Out of Chip) Symbol Parameter t MDC Period P t MDIO Set-Up to MDC (MDIO as Input) MD1 t MDIO Hold After MDC (MDIO as Input) MD2 t MDC to MDIO ...

Page 30

KS8721CL Supply Voltage RST_N Strap-In Value Symbol Parameter t Stable Supply Voltages to Reset High sr Reference Circuit for Strapping Option Configuration Figure 10 shows the reference circuit for strapping option pins. Reset Circuit Diagram Micrel recommendeds the following discrete ...

Page 31

KS8721CL Figure 13. Reference Circuit, Strapping Option Pins April 2005 3.3V 220Ω Pull-Up 10kΩ LED pin KS8721CL 3.3V 220Ω Pull-down LED pin KS8721CL 1kΩ Reference circuits for unmanaged programming through LED ports 31 Micrel, Inc. M9999-041405 ...

Page 32

KS8721CL Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristic Turns Ratio Open-Circuit ...

Page 33

... KS8721CL Package Information MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. ...

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