PIC12F683-I/MD Microchip Technology Inc., PIC12F683-I/MD Datasheet - Page 73

• Manufacturer Part Number: PIC12F683-I/MD
• Description: 8 PIN, 3.5KB FLASH, 128 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-I/MD

• A/d Inputs: 4-Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-Pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Serial Interface: None
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

11.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the GP2/AN2/T0CKI/INT/
COUT/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit, CCP1IF (PIR1<5>), is set.
FIGURE 11-2:
TABLE 11-2:
 2004 Microchip Technology Inc.
0Bh/
8Bh
0Ch
0Eh
0Fh
10h
1Ah
13h
14h
15h
8Ch
Legend:
Addr
GP2/CCP1
Special Event Trigger will:
• Clear TMR1H and TMR1L registers
• NOT set interrupt flag bit TMR1F (PIR1<0>)
• Set the GO/DONE bit (ADCON0<1>)
pin
Output Enable
TRISIO<2>
INTCON
PIR1
TMR1L
TMR1H
T1CON
CMCON1
CCPR1L
CCPR1H
CCP1CON
PIE1
Compare Mode
Name
— = unimplemented locations, read as ‘0’, u = unchanged, x = unknown.
Shaded cells are not used by the Capture, Compare or Timer1 module.
Q
Special Event Trigger
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
CCP1CON<3:0>
R
S
EEIE
Bit 7
EEIF
GIE
Mode Select
—
—
Output
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
Set Flag bit CCP1IF
ADIF
ADIE
Bit 6
PEIE
(PIR1<5>)
—
—
Match
CCP1IF
CCP1IE
CCPR1H CCPR1L
DC1B1
TMR1H
Bit 5
T0IE
—
Comparator
TMR1L
DC1B0
INTE
Bit 4
—
—
—
Preliminary
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
CMIE
GPIE
CMIF
Bit 3
—
11.2.1
The user must configure the GP2/AN2/T0CKI/INT/
COUT/CCP1 pin as an output by clearing the
TRISIO<2> bit.
11.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
11.2.3
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 pin is not affected.
The CCP1IF (PIR1<5>) bit is set, causing a CCP
interrupt (if enabled). See Register 11-1.
11.2.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts A/D conversion, if
enabled. This allows the CCPR1 register to effectively
be a 16-bit programmable period register for Timer1.
Note:
Note:
OSFIF
OSFIE
Bit 2
T0IF
—
CCP1 PIN CONFIGURATION
Clearing the CCP1CON register will
force
CCP1 compare output latch to the default
low level. This is not the GPIO data latch.
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The special event trigger from the CCP1
modules will not set interrupt flag bit
TMR1IF (PIR1<0>).
TMR2IF
TMR2IE
T1GSS CMSYNC ---- --10 ---- --10
Bit 1
INTF
the
TMR1IE 000- 0000 000- 0000
TMR1IF 000- 0000 000- 0000
GPIF
Bit 0
GP2/AN2/T0CKI/INT/COUT/
PIC12F683
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
POR, BOD
Value on
DS41211B-page 71
Value on
all other
Resets