PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 118

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87/88
The ADRESH:ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is
complete, the result is loaded into the A/D Result register
pair, the GO/DONE bit (ADCON0<2>) is cleared and
A/D Interrupt Flag bit, ADIF, is set. The block diagram of
the A/D module is shown in Figure 12-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 12.1 “A/D
Acquisition Requirements”. After this sample time
has elapsed, the A/D conversion can be started.
These steps should be followed for doing an A/D
conversion:
1.
FIGURE 12-1:
DS30487C-page 116
Configure the A/D module:
• Configure analog/digital I/O (ANSEL)
• Configure voltage reference (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Converter
A/D
A/D BLOCK DIAGRAM
(Reference
(Reference
Voltage)
Voltage)
V
V
REF
REF
-
+
(Input Voltage)
VCFG1:VCFG0
VCFG1:VCFG0
V
IN
AV
AV
DD
SS
CHS2:CHS0
2.
3.
4.
5.
6.
7.
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• SET PEIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
• Waiting for the A/D interrupt
Read A/D Result register pair
(ADRESH:ADRESL), clear bit ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as T
required before the next acquisition starts.
(with interrupts disabled); OR
110
101
100
011
010
001
000
AD
. A minimum wait of 2 T
 2005 Microchip Technology Inc.
RB7/AN6/PGD/T1OSI
RB6/AN5/PGC/T1OSO/T1CKI
RA4/AN4/T0CKI/C2OUT
RA3/AN3/V
RA2/AN2/CV
RA1/AN1
RA0/AN0
REF
REF
+/C1OUT
/V
REF
-
AD
is