PIC18F2520-I/SP Microchip Technology Inc., PIC18F2520-I/SP Datasheet - Page 121
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PIC18F2520-I/SP
Manufacturer Part Number
PIC18F2520-I/SP
Description
28 Pin, 32 KB Flash, 1536 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2520-ISP.pdf
(390 pages)
Specifications of PIC18F2520-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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Manufacturer
Quantity
Price
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Manufacturer:
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Quantity:
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Manufacturer:
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TABLE 10-9:
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
2004 Microchip Technology Inc.
PORTE
LATE
TRISE
ADCON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1:
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
MCLR/V
Legend:
Note 1:
Name
(2)
2:
2:
Pin
PP
/RE3
Implemented only when Master Clear functionality is disabled (MCLRE configuration bit = 0).
RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin
devices.
RE3 does not have a corresponding TRIS bit to control data direction.
(1)
Bit 7
IBF
—
—
—
PORTE I/O SUMMARY
Function
MCLR
RE0
AN5
RE1
AN6
RE2
AN7
RE3
WR
V
RD
CS
PP
Bit 6
OBF
—
—
—
Setting
TRIS
—
—
—
0
1
1
1
0
1
1
1
0
1
1
1
(2)
VCFG1
IBOV
Bit 5
I/O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
—
—
PIC18F2420/2520/4420/4520
Type
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
I/O
ST
ST
ST
ST
ST
PSPMODE
VCFG0
Preliminary
Bit 4
—
—
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
PSP read enable input (PSP enabled).
A/D input channel 5; default input configuration on POR.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
A/D input channel 6; default input configuration on POR.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
A/D input channel 7; default input configuration on POR.
External Master Clear input; enabled when MCLRE configuration bit is
set.
High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
PORTE<3> data input; enabled when MCLRE configuration bit is clear.
RE3
PCFG3
Bit 3
—
—
(1,2)
LATE Data Output Register
TRISE2
PCFG2
Bit 2
RE2
Description
TRISE1
PCFG1
Bit 1
RE1
TRISE0
PCFG0
Bit 0
DS39631A-page 119
RE0
on page
Values
Reset
52
51
52
52
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