KSZ8041TL Micrel Inc, KSZ8041TL Datasheet
KSZ8041TL
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KSZ8041TL Summary of contents
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... Micrel LinkMD TDR-based cable diagnostics permit identification of faulty copper cabling. The KSZ8041TL represents a new level of features and Functional Diagram KSZ8041TL/FTL LinkMD is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 ( ...
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... Back-to-Back mode support for 100Mbps repeater or media converter x MII interface support x RMII interface support with external 50MHz system clock (KSZ8041TL/FTL only) x SMII interface support with external 125MHz system clock and 12.5MHz sync clock from MAC (KSZ8041TL/FTL only) x MIIM (MDC/MDIO) management bus to 12.5MHz for ...
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... Changed polarity (swapped definition) of DUPLEX strapping pin. Removed DUPLEX strapping pin update to Register 4h – Auto-Negotiation Advertisement bits [8, 6]. Added Back-to-Back mode for KSZ8041TL. Added Symbol Error to MII/RMII Receive Error description and Register 15h – RXER Counter. Added a 100pF capacitor on REXT (pin 16) in Pin Description table. ...
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... Reduced MII (RMII) Data Interface (KSZ8041TL/FTL only)............................................................................................. 27 RMII Signal Definition (KSZ8041TL/FTL only) ................................................................................................................. 28 Reference Clock (REF_CLK) ..................................................................................................................................... 28 Transmit Enable (TX_EN)........................................................................................................................................... 28 Transmit Data [1:0] (TXD[1:0])................................................................................................................................... 28 Carrier Sense/Receive Data Valid (CRS_DV) ........................................................................................................... 28 Receive Data [1:0] (RXD[1:0]) .................................................................................................................................... 28 Receive Error (RX_ER)............................................................................................................................................... 28 Collision Detection ..................................................................................................................................................... 29 Serial MII (SMII) Data Interface (KSZ8041TL/FTL only) .................................................................................................. 29 December 2009 4 KSZ8041TL/FTL/MLL M9999-120909-1.2 ...
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... Reference Clock Connection Options .............................................................................................................................. 35 Reference Circuit for Power and Ground Connections .................................................................................................... 36 100Base-FX Fiber Operation (KSZ8041FTL only) ........................................................................................................... 37 Fiber Signal Detect ..................................................................................................................................................... 37 Far-End Fault............................................................................................................................................................... 37 Back-to-Back Media Converter......................................................................................................................................... 38 MII Back-to-Back Mode .............................................................................................................................................. 38 RMII Back-to-Back Mode (KSZ8041TL/FTL only) .................................................................................................... 39 Register Map........................................................................................................................................................................ 40 Register Description ........................................................................................................................................................... 40 (1) Absolute Maximum Ratings ............................................................................................................................................ 48 (2) Operating Ratings ...
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... Figure 7. 50MHz Oscillator Reference Clock for RMII Mode............................................................................................... 35 Figure 8. 125MHz Oscillator Reference Clock for SMII Mode ............................................................................................. 35 Figure 9. KSZ8041TL/FTL/MLL Power and Ground Connections....................................................................................... 36 Figure 10. KSZ8041TL/MLL and KSZ8041FTL Back-to-Back Media Converter................................................................. 38 Figure 11. MII SQE Timing (10Base-T) ............................................................................................................................... 50 Figure 12. MII Transmit Timing (10Base-T) ......................................................................................................................... 51 Figure 13. MII Receive Timing (10Base-T) .......................................................................................................................... 52 Figure 14 ...
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... Table 6. SMII TXD[0:7] Encoding Table .............................................................................................................................. 30 Table 7. SMII RX Bit Description.......................................................................................................................................... 31 Table 8. SMII RXD[0:7] Encoding Table .............................................................................................................................. 31 Table 9. MDI/MDI-X Pin Definition ....................................................................................................................................... 32 Table 10. KSZ8041TL/FTL/MLL Power Pin Description...................................................................................................... 36 Table 11. Copper and Fiber Mode Selection ....................................................................................................................... 37 Table 12. MII Signal Connection for MII Back-to-Back Mode .............................................................................................. 38 Table 13. RMII Signal Connection for RMII Back-to-Back Mode......................................................................................... 39 Table 14 ...
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... Micrel, Inc. Pin Configuration – KSZ8041TL GND 2 GND 3 GND 4 VDDA_1.8 5 VDDA_1.8 6 V1.8_OUT 7 VDDA_3.3 8 VDDA_3.3 9 RX- 10 RX+ 11 TX December 2009 KSZ8041TL 48-Pin TQFP 8 KSZ8041TL/FTL/MLL TXD1 / TXD[1] / SYNC TXD0 / TXD[ TXEN / TX_EN TXC INTRP VDD_1.8 GND RXER / RX_ER / ISO RXC RXDV / CRSDV / CONFIG2 VDDIO_3 ...
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... Pin Configuration – KSZ8041FTL GND 2 GND 3 GND 4 VDDA_1.8 5 VDDA_1.8 6 V1.8_OUT 7 VDDA_3.3 8 VDDA_3.3 9 RX- 10 RX+ 11 TX December 2009 KSZ8041FTL 48-Pin TQFP 9 KSZ8041TL/FTL/MLL TXD1 / TXD[1] / SYNC TXD0 / TXD[ TXEN / TX_EN TXC INTRP VDD_1.8 GND RXER / RX_ER / ISO RXC RXDV / CRSDV / CONFIG2 VDDIO_3.3 VDDIO_3 M9999-120909-1 ...
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... SMII Mode: 125MHz +/-100ppm (oscillator, or external clock only) I/O Set physical transmit output current Connect a 6.49K: resistor in parallel with a 100pF capacitor to ground on this pin. See KSZ8041TL-FTL reference schematics. Gnd Ground I/O Management Interface (MII) Data I/O This pin requires an external 4.7K: pull-up resistor. ...
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... The pull-up/pull-down value is latched as CONFIG0 during power-up / reset. See “Strapping Options” section for details. Ipd/O MII Mode: Carrier Sense Output / Config. Mode: The pull-up/pull-down value is latched as CONFIG1 during power-up / reset. See “Strapping Options” section for details. 11 KSZ8041TL/FTL/MLL (2) / (3) / (4) / Transmit Clock Output Transmit Clock Input ...
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... The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as follows. LED mode = [00] Link/Activity Pin State No Link H Link L Activity Toggle LED mode = [01] Link Pin State No Link H Link L LED mode = [10] Reserved LED mode = [11] Reserved 12 KSZ8041TL/FTL/MLL LED Definition OFF ON Blinking LED Definition OFF ON LED Definition OFF ON Blinking LED Definition OFF ON M9999-120909-1.2 ...
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... LED mode = [00] Speed Pin State 10BT H 100BT L LED mode = [01] Activity Pin State No Activity H Activity Toggle LED mode = [10] Reserved LED mode = [11] Reserved - No connect - No connect - No connect 13 KSZ8041TL/FTL/MLL LED Definition OFF ON LED Definition OFF Blinking LED Definition OFF ON LED Definition OFF Blinking M9999-120909-1.2 ...
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... Chip Reset (active low connect Ipd FXSD: Signal Detect for 100Base-FX fiber mode FXEN: Fiber Enable for 100Base-FX fiber mode If FXEN=0, fiber mode is disabled. PHY is in copper mode. The default is “0”. See “100Base-FX Operation” section for details. 14 KSZ8041TL/FTL/MLL M9999-120909-1.2 ...
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... Micrel, Inc. Strapping Options- KSZ8041TL/FTL Pin Number Pin Name Type 22 PHYAD2 21 PHYAD1 20 PHYAD0 27 CONFIG2 41 CONFIG1 40 CONFIG0 29 ISO 43 SPEED (KSZ8041TL) 43 SPEED / (KSZ8041FTL) no FEF December 2009 (1) Pin Function Ipd/O The PHY Address is latched at power-up / reset and is configurable to any value from Ipd/O The default PHY Address is 00001. ...
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... During power-up / reset, this pin value is latched into register 0h bit 12. Ipu/O If copper mode (FXEN=0), pin strap-in is Nway Auto-Negotiation Enable. Pull-up (default) = Enable Auto-Negotiation Pull-down = Disable Auto-Negotiation During power-up / reset, this pin value is latched into register 0h bit 12. If fiber mode (FXEN=1), this pin configuration is always strapped to disable Auto- Negotiation. 16 KSZ8041TL/FTL/MLL M9999-120909-1.2 ...
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... Micrel, Inc. Pin Configuration –KSZ8041MLL 1 GND 2 GND 3 GND 4 VDDA_1.8 5 VDDA_1.8 6 V1.8_OUT 7 VDDA_3.3 8 VDDA_3.3 9 RX- 10 RX+ 11 TX- 12 TX+ December 2009 KSZ8041MLL 48-Pin LQFP 17 KSZ8041TL/FTL/MLL TXD1 36 TXD0 35 TXEN 34 TXC 33 INTRP 32 VDD_1.8 31 GND 30 RXER / 29 ISO RXC 28 RXDV / 27 CONFIG2 VDDIO_3.3 26 VDDIO_3 M9999-120909-1.2 ...
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... See “Strapping Options” section for details. Ipu/O MII Mode: Receive Data Output[0] Config Mode: Latched as DUPLEX (register 0h, bit 8) during power-up / reset. See “Strapping Options” section for details. Gnd Ground P 3.3V digital 3.3V digital KSZ8041TL/FTL/MLL (2) / (2) / (2) / (2) / M9999-120909-1.2 ...
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... The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as follows. LED mode = [00] Link/Activity Pin State No Link H Link L Activity Toggle LED mode = [01] Link Pin State No Link H Link L LED mode = [10] Reserved LED mode = [11] Reserved 19 KSZ8041TL/FTL/MLL (3) (3) (3) / (3) / LED Definition OFF ON Blinking LED Definition OFF ON M9999-120909-1.2 ...
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... The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as follows. LED mode = [00] Speed Pin State 10BT H 100BT L LED mode = [01] Activity Pin State No Activity H Activity Toggle LED mode = [10] Reserved LED mode = [11] Reserved - No connect - No connect - No connect I Chip Reset (active low connect 20 KSZ8041TL/FTL/MLL LED Definition OFF ON LED Definition OFF Blinking M9999-120909-1.2 ...
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... Pull-down = Full Duplex During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex Mode. Ipu/O Nway Auto-Negotiation Enable Pull-up (default) = Enable Auto-Negotiation Pull-down = Disable Auto-Negotiation During power-up / reset, this pin value is latched into register 0h bit 12. 21 KSZ8041TL/FTL/MLL M9999-120909-1.2 ...
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... On the media side, the KSZ8041TL supports 10Base-T and 100Base-TX with HP auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables. The KSZ8041TL offers a choice of MII, RMII, or SMII data interface connection to a MAC processor. The MII management bus option gives the MAC processor complete access to the KSZ8041TL control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change ...
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... If auto-negotiation is not supported or the KSZ8041TL/FTL/MLL link partner is forced to bypass auto-negotiation, the KSZ8041TL/FTL/MLL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ8041TL/FTL/MLL to establish link by listening for a fixed signal protocol in the absence of auto- negotiation advertisement protocol. ...
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... Force Link Setting Yes Bypass Auto Negotiation and Set Link Mode December 2009 N Parallel Operation o Attempt Auto Listen for 100BASE-TX Negotiation Idles Join Flow Link Mode Set ? Yes Link Mode Set Figure 1. Auto-Negotiation Flow Chart 24 KSZ8041TL/FTL/MLL Listen for 10BASE-T Link Pulses No M9999-120909-1.2 ...
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... INTRP (pin 32 optional interrupt signal that is used to inform the external controller that there has been a status update to the KSZ8041TL/FTL/MLL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used to enable and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits, and are used to indicate which interrupt conditions have occurred ...
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... Micrel, Inc. MII Signal Definition The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information. Direction MII (with respect to PHY, Signal Name KSZ8041TL/FTL/MLL signal) TXC Output TXEN Input TXD[3:0] Input RXC Output RXDV Output ...
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... Provides independent 2-bit wide (di-bit) transmit and receive data paths. x Contains two distinct groups of signals: one for transmission and the other for reception. The KSZ8041TL/FTL is configured in RMII mode after it is power-up or reset with the following MHz reference clock connected to REFCLK (pin 15). ...
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... Micrel, Inc. RMII Signal Definition (KSZ8041TL/FTL only) The following table describes the RMII signals. Refer to RMII Specification for detailed information. Direction RMII (with respect to PHY, Signal Name KSZ8041TL/FTL signal) REF_CLK Input TX_EN Input TXD[1:0] Input CRS_DV Output RXD[1:0] Output RX_ER Output Reference Clock (REF_CLK) REF_CLK is sourced by the MAC or system board ...
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... Uses 12.5MHz sync pulse provided by the MAC. x Provides independent single-bit wide transmit and receive data paths for data and control information. The KSZ8041TL/FTL is configured in SMII mode after it is power-up or reset with the following 125MHz reference clock connected to CLOCK (pin 15 12.5MHz sync pulse connected to SYNC (pin 36). ...
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... See SMII TXD[0:7] Encoding Table (below) Table 5. SMII TX Bit Description TXD1 TXD2 TXD3 Speed Duplex Link 0=10M 0=Half 0=Down 1=100M 1=Full 1=Up Table 6. SMII TXD[0:7] Encoding Table 30 KSZ8041TL/FTL/MLL TXD4 TXD5 TXD6 TXD7 TXD4 TXD5 TXD6 Jabber 1 1 0=No 1=Yes M9999-120909-1.2 TXD7 1 ...
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... See SMII RXD[0:7] Encoding Table (below) Table 7. SMII RX Bit Description RXD1 RXD2 RXD3 Speed Duplex Link 0=10M 0=Half 0=Down 1=100M 1=Full 1=Up Table 8. SMII RXD[0:7] Encoding Table 31 KSZ8041TL/FTL/MLL RXD4 RXD5 RXD6 RXD7 RXD4 RXD5 RXD6 Upper False Jabber Nibble Carrier 0=No Detected 1=Yes ...
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... HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable between the KSZ8041TL/FTL/MLL and its link partner. This feature allows the KSZ8041TL/FTL/MLL to use either type of cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8041TL/FTL/MLL accordingly ...
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... December 2009 10/100 Ethernet Media Dependent Interface 1 Crossover Receive Pair Cable Transmit Pair Modular Connector (RJ-45) HUB (Repeater or Switch) Figure 5. Typical Crossover Cable Connection 33 KSZ8041TL/FTL/MLL 10/100 Ethernet Media Dependent Interface 1 Receive Pair Transmit Pair Modular Connector (RJ-45) HUB (Repeater or Switch) M9999-120909-1.2 ...
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... Power saving mode is disabled by writing a zero to register 1Fh bit 10. Power Down Mode This mode is used to power down the entire KSZ8041TL/FTL/MLL device when it is not in use. Power down mode is enabled by writing a one to register 0h bit 11. In the power down state, the KSZ8041TL/FTL/MLL disables all internal functions, except for the MII management interface ...
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... Micrel, Inc. Reference Clock Connection Options A crystal or clock source, such as an oscillator, is used to provide the reference clock for the KSZ8041TL/FTL/MLL. The following figure illustrates how to connect the 25MHz crystal and oscillator reference clock for MII mode. 22pF 22pF 22pF 22pF 25MHz XTAL +/-50ppm Figure 6 ...
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... Micrel, Inc. Reference Circuit for Power and Ground Connections The KSZ8041TL/FTL/MLL is a single 3.3V supply device with a built-in 1.8V low noise regulator. The power and ground connections are shown in the following figure and table. Figure 9. KSZ8041TL/FTL/MLL Power and Ground Connections Power Pin Pin Number V1 ...
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... By default, FEF is enabled. FEF is disabled by strapping “no FEF” (pin 43) low. See “Strapping Options” section for detail. December 2009 Mode Copper mode Fiber mode No signal detected Far-End Fault generated (if enabled) Fiber mode Signal detected Table 11. Copper and Fiber Mode Selection 37 KSZ8041TL/FTL/MLL M9999-120909-1.2 ...
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... Micrel, Inc. Back-to-Back Media Converter A KSZ8041TL/MLL and a KSZ8041FTL can be connected back-to-back to provide a low cost media converter solution. In back-to-back mode, media conversion is between 100Base-TX copper and 100Base-FX fiber. On the copper side, link up at 10Base-T is not allowed, and is blocked during auto-negotiation. Figure 10. KSZ8041TL/MLL and KSZ8041FTL Back-to-Back Media Converter ...
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... This KSZ8041TL/FTL feature functions as follows the KSZ8041TL copper side, RXD2 (pin 21) indicates if there is energy detected at the receive inputs of the copper port. RXD2 outputs a low if there is no energy detected (cable disconnected), and outputs a high if there is energy detected (cable connected). ...
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... Electrical isolation of PHY from MII and 0 = Normal operation 0.9 Restart Auto Restart auto-negotiation process Negotiation 0 = Normal operation. This bit is self-cleared after a ‘1’ is written to it. December 2009 ® Control/Status TX+/TX- 40 KSZ8041TL/FTL/MLL (1) Default Mode RW/ Set by SPEED strapping pin. See “Strapping Options” section for details. RW Set by NWAYEN strapping pin. See “ ...
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... Assigned to the 3rd through 18th bits of the Number Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) December 2009 (1) Default Mode RW Inverse of DUPLEX strapping pin value. See “Strapping Options” section for details 000_000 0000 RO/ RO/LL 0 RO/ 0022h 41 KSZ8041TL/FTL/MLL M9999-120909-1.2 ...
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... Asymmetric & Symmetric PAUSE December 2009 (1) Default Mode th bits of the RO 0001_01 RO 01_0001 RO Indicate silicon revision Set by SPEED strapping pin. See “Strapping Options” section for details. RW Set by SPEED strapping pin. See “Strapping Options” section for details 0_0001 KSZ8041TL/FTL/MLL M9999-120909-1.2 ...
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... Logic zero 7.10:0 Message Field 11-bit wide field to encode 2048 messages Register 8h – Link Partner Next Page Ability 8.15 Next Page 1 = Additional Next Page(s) will follow 0 = Last page December 2009 capability capability capability word equaled logic one 43 KSZ8041TL/FTL/MLL (1) Default Mode 0_0001 ...
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... Remote Fault 1 = Enable Remote Fault Interrupt Interrupt 0 = Disable Remote Fault Interrupt Enable December 2009 word equal to logic zero word equal to logic one (random latency) frame to MII output for fixed latency sending frame (starting with SFD) to MII output Interrupt 44 KSZ8041TL/FTL/MLL (1) Default Mode 000_0000_0000 ...
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... Polarity 0 = Polarity is not reversed 1 = Polarity is reversed December 2009 has completed, this bit is self-cleared. has completed and the status information is valid for read. cable cable LED1 : Speed LED0 : Link/Activity LED1 : Activity LED0 : Link 45 KSZ8041TL/FTL/MLL (1) Default Mode RW 0 RO/SC 0 RO/SC 0 RO/SC 0 RO/SC 0 RO/SC ...
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... Negotiation 0 = Auto-negotiation process not completed Complete 1f.6 Enable Pause 1 = Flow control capable (Flow Control flow control capability December 2009 Transmit on TX+/- (pins 12,11) and Receive on RX+/- (pins 10,9) Transmit on RX+/- (pins 10,9) and Receive on TX+/- (pins 12,11) pair 46 KSZ8041TL/FTL/MLL (1) Default Mode ...
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... Enable SQE 1 = Enable SQE test test 0 = Disable SQE test 1f.0 Disable Data 1 = Disable scrambler Scrambling 0 = Enable scrambler Note Read/Write Read only Self-cleared Latch high Latch low. December 2009 (1) Default Mode 000 KSZ8041TL/FTL/MLL M9999-120909-1.2 ...
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... OL Each LED pin (LED0, LED1) 100Ÿ termination across differential output 100Ÿtermination across differential output Peak-to-peak 100Ÿ termination across differential output Peak-to-peak 5MHz square wave 48 KSZ8041TL/FTL/MLL ( .......................... +3.135V to +3.465V DDIO_3.3, DDA_3.3 , Commercial) ........ 0°C to +70° Industrial)..........-40°C to +85°C A Max) ................. 125° ...
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... Specification for packaged product only Current consumption is for the single 3.3V supply KSZ8041TL/FTL/MLL device only, and includes the 1.8V supply voltage (V that is provided by the KSZ8041TL/FTL/MLL. The PHY port’s transformer consumes an additional 45mA @ 3.3V for 100Base-TX and 70mA @ 3.3V for 10Base-T. December 2009 ...
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... SQEP Figure 11. MII SQE Timing (10Base-T) Description TXC period TXC pulse width low TXC pulse width high COL (SQE) delay after TXEN de-asserted COL (SQE) pulse duration Table 14. MII SQE Timing (10Base-T) Parameters 50 KSZ8041TL/FTL/MLL Min Typ Max Unit 400 ns 200 ns 200 ns 2 ...
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... TXD[3:0] setup to rising edge of TXC TXEN setup to rising edge of TXC TXD[3:0] hold from rising edge of TXC TXEN hold from rising edge of TXC TXEN high to CRS asserted latency TXEN low to CRS de-asserted latency Table 15. MII Transmit Timing (10Base-T) Parameters 51 KSZ8041TL/FTL/MLL CRS2 Min ...
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... Figure 13. MII Receive Timing (10Base-T) Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) output delay from rising edge of RXC CRS to (RXD[3:0], RXER, RXDV) latency Table 16. MII Receive Timing (10Base-T) Parameters 52 KSZ8041TL/FTL/MLL Min Typ Max Unit 400 ns 200 ns 200 ns ...
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... TXD[3:0] setup to rising edge of TXC TXEN setup to rising edge of TXC TXD[3:0] hold from rising edge of TXC TXEN hold from rising edge of TXC TXEN high to CRS asserted latency TXEN low to CRS de-asserted latency Table 17. MII Transmit Timing (100Base-TX) Parameters 53 KSZ8041TL/FTL/MLL Min Typ Max Unit ...
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... Figure 15. MII Receive Timing (100Base-TX) Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) output delay from rising edge of RXC CRS to RXDV latency CRS to RXD[3:0] latency CRS to RXER latency Table 18. MII Receive Timing (100Base-TX) Parameters 54 KSZ8041TL/FTL/MLL Min Typ Max Unit ...
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... December 2009 tcyc t1 t2 Figure 16. RMII Timing – Data Received from RMII tcyc tod Figure 17. RMII Timing – Data Input to RMII Description Min Clock cycle Setup time 4 Hold time 2 Output delay 3 Table 19. RMII Timing Parameters 55 KSZ8041TL/FTL/MLL Typ Max Unit M9999-120909-1.2 ...
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... Timing Parameter December 2009 Figure 18. SMII Timing – Data Received from SMII Figure 19. SMII Timing – Data Input to SMII Description Min Setup time 1.5 Hold time 1.0 Output delay 4.0 Table 20. SMII Timing Parameters 56 KSZ8041TL/FTL/MLL Typ Max Unit ns ns 5.0 ns M9999-120909-1.2 ...
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... FLP Burst to FLP Burst FLP Burst width Clock/Data Pulse width Clock Pulse to Data Pulse Clock Pulse to Clock Pulse Number of Clock/Data Pulse per FLP Burst rst Min Typ Max 100 55.5 64 69.5 111 128 139 17 33 KSZ8041TL/FTL/MLL lse Units µs µs M9999-120909-1.2 ...
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... MDIO (PHY input) hold from rising edge of MDC MD2 t MDIO (PHY output) delay from rising edge of MDC MD3 December 2009 MD1 MD2 Valid Data t MD3 Figure 21. MDC/MDIO Timing Table 22. MDC/MDIO Timing Parameters 58 KSZ8041TL/FTL/MLL Valid Data Valid Data Min Typ Max Unit 400 222 ns M9999-120909-1.2 ...
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... Micrel, Inc. Reset Timing The KSZ8041TL/FTL/MLL reset timing requirement is summarized in the following figure and table. Supply Voltage RST# Strap-In Value Strap-In / Output Pin Parameter After the de-assertion of reset recommended to wait a minimum of 100μs before starting programming on the MIIM (MDC/MDIO) Interface. December 2009 ...
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... Micrel, Inc. Reset Circuit The following reset circuit is recommended for powering up the KSZ8041TL/FTL/MLL if reset is triggered by the power supply. The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or FPGA). At power-on-reset and D1 provide the necessary ramp rise time to reset the KSZ8041TL/FTL/MLL device. The RST_OUT_n from CPU/FPGA provides the warm reset after power up ...
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... The following figure shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strapping pins. December 2009 Pull-up KSZ8041TL/FTL/MLL LED pin Float KSZ8041TL/FTL/MLL LED pin Pull-down KSZ8041TL/FTL/MLL LED pin Figure 25. Reference Circuits for LED Strapping Pins 61 KSZ8041TL/FTL/MLL 3.3V 3.3V 3.3V M9999-120909-1.2 ...
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... SI-46001 SI-50170 LF8505 LF-H41S H1102 H1260 HB726 TLA-6T718 Table 25. Qualified Single Port Magnetics Value 25 r50 20 40 Table 26. Typical Reference Crystal Characteristics 62 KSZ8041TL/FTL/MLL Test Condition 100mV, 100kHz, 8mA 1MHz (min.) 0MHz – 65MHz Auto MDI-X Number of Port Yes 1 Yes 1 Yes 1 Yes 1 Yes ...
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... Micrel, Inc. Package Information 48-Pin LQFP December 2009 48-Pin (7mm x 7mm) LQFP Package 63 KSZ8041TL/FTL/MLL M9999-120909-1.2 ...
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... Micrel, Inc. 48-Pin TQFP Note: ALL DIMENSIONS ARE IN MILLIMETERS. December 2009 48-Pin (7mm x 7mm) TQFP Package 64 KSZ8041TL/FTL/MLL M9999-120909-1 ...
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... A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to December 2009 fully indemnify Micrel for any damages resulting from such use or sale. © 2008 Micrel, Incorporated. 65 KSZ8041TL/FTL/MLL M9999-120909-1.2 ...