CS8130-CS Cirrus Logic Inc, CS8130-CS Datasheet - Page 26

• Manufacturer Part Number: CS8130-CS
• Description: IC IR TRANSCEIVER 2-5V 20-SSOP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8130-CS

• Mounting Type: Surface Mount
• Voltage - Supply: 2.7 V ~ 5.5 V
• Package / Case: 20-SSOP
• Logic Case Style: SSOP
• No. Of Pins: 20
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5.5V
• Transceiver Type: Infrared
• Driver Case Style: SSOP
• Leaded Process Compatible: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1161 - BOARD EVAL FOR CS8130
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1203-5

Digital Pins
RXD - Receiver Data Output
TXD - Transmit Data Input
D/C - Data/Control Mode Input
FORM/BSY - Received Data Format Output/Busy Signal Output
PWRDN - Power Down Control Input
RESET - Reset Input
XTALIN, XTALOUT - Crystal Connections
EXTCLK - External Clock Input or Output
CLKFR - Clock Frequency Select Input
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Receiver output data. Normally connected to RxD on the UART.
Transmitter input data. Normally connected to TxD on the UART.
The D/C pin determines whether the input data on TXD is treated as data to be transmitted via
the LED, or as control information to set up the CS8130 internal registers. The D/C pin also
can act as a power down control.
If auto format detect mode is enabled, this pin indicates the format of the incoming data.
FORM is low for ASK format data, and high for IRDA/HPSIR format data.
In TV remote data mode (Mode 3), this pin becomes a handshake signal to the UART.
FORM/BSY low means OK to send a character. FORM/BSY high means "I am busy, do not
send another character".
PWRDN low places the CS8130 into a very low power consumption "off" state.
RESET low places all the internal logic into a known state. All the control register bits are
forced high or low, as defined in the register definition section. If the crystal oscillator is in use,
then RESET must be held low for >25 ms, with PWRDN high and power applied. If an
external clock is used, then the RESET pulse can be short (>1 s).
To use the internal oscillator, connect either a 3.6864 MHz or a 1.8432 MHz crystal between
XTALOUT and XTALIN. If using an external clock, connect XTALIN to DGND.
If no crystal is present on XTALIN and XTALOUT, EXTCLK becomes an input. A
3.6864 MHz or 1.8432 MHz clock should be connected to EXTCLK. XTALIN should be
connected to DGND.
If a crystal is present on XTALIN and XTALOUT, EXTCLK becomes an output. EXTCLK will
output the same frequency as the crystal. The EXTCLK output driver may be disabled to
conserve power.
Tie CLKFR to ground to select a 3.6864 MHz clock. Connect CLKFR to the VD+ pin to select
a 1.8432 MHz clock.
CS8130
CS8130
DS134PP2
DS134F1