DP8390DN National Semiconductor, DP8390DN Datasheet - Page 15

• Manufacturer Part Number: DP8390DN
• Description: IC NIC (NETWORK INT CTRL)48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8390DN

• Controller Type: Network Interface Controller (NIC)
• Voltage - Supply: 5V
• Current - Supply: 40mA
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Interface: -
• Other names: *DP8390DN

9 0 Remote DMA
byte has entered the FIFO thus with an 8 byte threshold
the NIC issues Bus Request (BREQ) when the 9th byte has
entered the FIFO For Word Mode BREQ is not generated
until the n
word threshold (equivalent to 8 byte threshold) BREQ is
issued when the 10th byte has entered the FIFO The two
graphs the figures above indicate the maximum allowable
bus latency for Word and Byte transfer modes
The FIFO at the Beginning of Transmit
Before transmitting the NIC performs a prefetch from mem-
ory to load the FIFO The number of bytes prefetched is the
programmed FIFO threshold The next BREQ is not issued
until after the NIC actually begins trasmitting data i e after
SFD The Transmit Prefetch diagram illustrates this process
SEND PACKET COMMAND
The Remote DMA channel can be automatically initialized
to transfer a single packet from the Receive Buffer Ring
Maximum Bus Latency for Byte Mode
a
2 bytes have entered the FIFO Thus with a 4
(Continued)
TL F 8582 – 98
Transmit Prefetch Timing
15
The CPU begins this transfer by issuing a ‘‘Send Packet’’
Command The DMA will be initialized to the value of the
Boundary Pointer Register and the Remote Byte Count
Register pair (RBCR0 RBCR1) will be initialized to the value
of the Receive Byte Count fields found in the Buffer Header
of each packet After the data is transferred the Boundary
Pointer is advanced to allow the buffers to be used for new
receive packets The Remote Read will terminate when the
Byte Count equals zero The Remote DMA is then prepared
to read the next packet from the Receive Buffer Ring If the
DMA pointer crosses the Page Stop Register it is reset to
the Page Start Address This allows the Remote DMA to
remove packets that have wrapped around to the top of the
Receive Buffer Ring
Note 1 In order for the NIC to correctly execute the Send Packet Com-
Note 2 The Send Packet command cannot be used with 68000 type proc-
mand the upper Remote Byte Count Register (RBCR1) must first
be loaded with 0FH
essors
Maximum Bus Latency for Word Mode
TL F 8582 – A0
TL F 8582 – 99