FW82443BXSL2VH Intel, FW82443BXSL2VH Datasheet
FW82443BXSL2VH
Specifications of FW82443BXSL2VH
Available stocks
Related parts for FW82443BXSL2VH
FW82443BXSL2VH Summary of contents
Page 1
... Intel 440BX AGPset: 82443BX Host Bridge/Controller Datasheet April 1998 Order Number: 290633-001 ...
Page 2
... Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...
Page 3
... Intel 82443BX Features • Processor/host bus support — Optimized for Pentium processor at 100 MHz system bus frequency; Support for 66 MHz — Supports full symmetric Multiprocessor (SMP) Protocol for up to two processors; I/O APIC related buffer management support (WSC# signal) — In-order transaction and dynamic deferred transaction support — ...
Page 4
... Intel 440BX AGPset platform is based on the 82371EB (PIIX4E), a highly integrated version of the Intel’s PCI-ISA bridge family. The Intel Pentium II processor platforms; providing full support for all system suspend modes and segmented power planes. Intel 82443BX Simplified Block Diagram CPURST# ...
Page 5
Contents 1 Architectural Overview ...............................................................................................1-1 2 Signal Description ......................................................................................................2-1 2.1 Host Interface Signals...................................................................................2-1 2.2 DRAM Interface ............................................................................................2-3 2.3 PCI Interface (Primary) .................................................................................2-5 2.4 Primary PCI Sideband Interface ...................................................................2-6 2.5 AGP Interface Signals...................................................................................2-7 2.6 Clocks, Reset, and Miscellaneous ................................................................2-9 2.7 Power-Up/Reset ...
Page 6
ESMRAMC—Extended System Management RAM Control 3.3.23 RPS—SDRAM Row Page Size Register (Device 0)......................3-30 3.3.24 SDRAMC—SDRAM Control Register (Device 0) ..........................3-30 3.3.25 PGPOL—Paging Policy Register (Device 0) .................................3-32 3.3.26 PMCR—Power Management Control Register (Device 0) ............3-33 3.3.27 SCRR—Suspend CBR Refresh ...
Page 7
Functional Description ...............................................................................................4-1 4.1 System Address Map....................................................................................4-1 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.2 Host Interface..............................................................................................4-10 4.2.1 4.2.2 4.2.3 4.2.4 4.3 DRAM Interface ..........................................................................................4-14 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.4 PCI Interface ...............................................................................................4-24 4.5 AGP Interface .............................................................................................4-24 4.6 Data Integrity ...
Page 8
... Three-DIMM SDRAM Configuration ...........................................................4-17 4-4 Three-SODIMMs EDO Configuration .........................................................4-18 4-5 Three-SODIMMs SDRAM Configuration ....................................................4-19 4-6 Typical Intel 4-7 Reset CPURST Desktop or Mobile System When PCIRST# Asserted .....................................................................................4-33 4-8 External Glue Logic Drives CPU Clock Ratio Straps ..................................4-34 5-1 82443BX Pinout (Top View–left side) ...........................................................5-2 5-2 82443BX Pinout (Top View– ...
Page 9
Tables 2-1 Host Interface Signals...................................................................................2-1 2-2 Host Signals Not supported by the 82443BX................................................2-3 2-3 DRAM Interface Signals................................................................................2-3 2-4 Primary PCI Interface Signals.......................................................................2-5 2-5 Primary PCI Sideband Interface Signals.......................................................2-6 2-6 AGP Interface Signals...................................................................................2-7 2-7 Clocks, Reset, and Miscellaneous ................................................................2-9 2-8 Power ...
Page 10
...
Page 11
... Mobile and “Deep Green” Desktop power management support Figure 1-1 shows a block diagram of a typical platform based on the Intel 82443BX host bus interface supports up to two Pentium II processors at the maximum bus frequency of 100 MHz. The physical interface design is based on the GTL+ specification optimized for the desktop ...
Page 12
... Architectural Overview ® Figure 1-1. Intel 440BX AGPset System Block Diagram Video - DVD - Camera - VCR Display TV Video BIOS Host Interface The Pentium II processor supports a second level cache via a back-side bus (BSB) interface. All control for the L2 cache is handled by the processor. The 82443BX provides bus control signals and address paths for transfers between the processors front-side bus (host bus), PCI bus, AGP and main memory ...
Page 13
... DRAM Speeds for EDO and 100/66 MHz for synchronous memory (SDRAM). ® The Intel 440BX AGPset also provides DIMM plug-and-play support via Serial Presence Detect (SPD) mechanism using the SMBus interface. The 82443BX provides optional data integrity features including ECC in the memory array. During reads from DRAM, the 82443BX provides error checking and correction of the data ...
Page 14
...
Page 15
Signal Description This chapter provides a detailed description of 443BX signals. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of a signal name indicates that the active, or asserted state ...
Page 16
Signal Description Table 2-1. Host Interface Signals (Sheet Name Type I/O ADS# GTL+ I/O BNR# GTL+ O BPRI# GTL+ O BREQ0# GTL+ I/O DBSY# GTL+ O DEFER# GTL+ I/O DRDY# GTL+ I/O HIT# GTL+ I/O HITM# GTL+ ...
Page 17
... Table 2-2 lists the CPU bus interface signals which are NOT supported by the Intel AGPset. Table 2-2. Host Signals Not supported by the 82443BX Signal A[35:32]# Address AERR# Address Parity Error AP[1:0]# Address Parity BINIT# Bus Initialization DEP[7:0]# Data Bus ECC/Parity IERR# ...
Page 18
Signal Description Table 2-3. DRAM Interface Signals (Sheet Name Type GCKE/CKE1 CMOS SRAS[B,A]# CMOS CKE0/FENA CMOS SCAS[B,A]# CMOS MAA[13:0] MAB[12:11]# CMOS MAB[13,10] MAB[9:0]# WEA# WEB# CMOS MD [63:0] CMOS MECC[7:0] CMOS 2-4 Global CKE (SDRAM): Global CKE ...
Page 19
PCI Interface (Primary) Table 2-4. Primary PCI Interface Signals (Sheet Name Type I/O AD[31:0] PCI I/O DEVSEL# PCI I/O FRAME# PCI I/O IRDY# PCI I/O C/BE[3:0]# PCI I/O PAR PCI I/O PLOCK# PCI I/O TRDY# PCI ...
Page 20
Signal Description Table 2-4. Primary PCI Interface Signals (Sheet Name Type I/O SERR# PCI I/O STOP# PCI NOTE: 1. All PCI interface signals conform to the PCI Rev 2.1 specification. 2.4 Primary PCI Sideband Interface Table 2-5. ...
Page 21
AGP Interface Signals There are 17 new signals added to the normal PCI group of signals that together constitute the AGP interface. The sections below describe their operation and use, and are organized in five groups: • AGP Addressing ...
Page 22
Signal Description Table 2-6. AGP Interface Signals (Sheet Name Type I/O ADSTB_A AGP I/O ADSTB_B AGP I SBSTB AGP I/O GFRAME# AGP I/O GIRDY# AGP I/O GTRDY# AGP I/O GSTOP# AGP I/O GDEVSEL# AGP I GREQ# AGP ...
Page 23
PCI signals are redefined when used in AGP transactions carried using AGP protocol extension. For transactions on the AGP interface carried using PCI protocol these signals completely preserve PCI semantics. The exact role of all PCI signals during AGP ...
Page 24
Signal Description Table 2-9. Reference Pins Name GTLREF[B:A] GTL Buffer voltage reference input VTT[B:A] GTL Threshold voltage for early clamps VCC Power pin @ 3.3V VSS Ground REF5V PCI 5V reference voltage (for 5V tolerant buffers) AGPREF External Input Reference ...
Page 25
Table 2-10. Strapping Options Register Signal Name[bit] MAB13# MAB12# NBXCFG[13] MAB11# NBXCFG[2] MAB10 PMCR[3] MAB9# PMCR[1] MAB8# MAB7# DRAMC[5] MAB6# none A[15]# none A7# none NOTE: 1. Proper strapping must be used to define logical values for these signals. Default ...
Page 26
...
Page 27
... In addition to reserved bits within a register, the 82443BX contains address locations in the configuration space of the Host-to-PCI Bridge entity that are marked either "Reserved" or “Intel Reserved”. The 82443BX responds to accesses to “Reserved” address locations by completing the host cycle. When a “Reserved” register location is read, a zero value is returned. (“Reserved” ...
Page 28
... Register Description 82443BX. Registers that are marked as “Intel Reserved” must not be modified by system software. Writes to “Intel Reserved” registers may cause system failure. Reads to “Intel Reserved” registers may return a non-zero value. Software should not write to reserved configuration locations in the device-specific region (above address offset 3Fh) Upon reset, the 82443BX sets its internal configuration registers to predetermined default states ...
Page 29
Bit Configuration Enable (CFGE). When this bit is set to 1 accesses to PCI configuration space are 31 enabled. If this bit is reset to 0 accesses to PCI configuration space are disabled. 30:24 Reserved. Bus Number. When the Bus ...
Page 30
Register Description Accesses to this register are controlled by the Power Management Control Register (Offset 7Ah). When bit 6 of the PMCR is set to ‘1’, the ACPI Register at I/O location 0022h is enabled. When bit 6 is set ...
Page 31
Figure 3-1. 82443BX PCI Bus Hierarchy AGP Device 3.2.1 Configuration Space Mechanism Overview The 82443BX supports two bus interfaces: PCI (referenced as Primary PCI) and AGP (referenced as AGP). The AGP interface is treated as a second PCI bus from ...
Page 32
Register Description 3.2.3 PCI Bus Configuration Mechanism Overview The PCI Bus defines a slot based "configuration space" that allows each device to contain functions with each function containing up to 256 8-bit configuration registers. The PCI specification ...
Page 33
Mapping of Configuration Cycles on AGP From the AGPset configuration perspective, AGP is seen as another PCI bus interface residing on a Secondary Bus side of the “virtual” PCI-to-PCI bridge referred to as the 82443BX Host- AGP bridge. On ...
Page 34
... DRAM Timing Programmable Attribute Map (7 registers) DRAM Row Boundary (8 registers) Fixed DRAM Hole Control Memory Buffer Strength Control Reserved Intel Reserved System Management RAM Control Extended System Management RAM Control. SDRAM Row Page Size SDRAM Control Register Paging Policy Register Power Management Control Register ...
Page 35
... F8–FBh — FC–FFh — NOTES: 1. The ‘S’ symbol represents the strapping option. 2. Write operations must not be attempted to the Intel Reserved registers. 82443BX Host Bridge Datasheet Register Name Error Address Pointer Register Reserved Error Command Register Error Status Register Reserved ...
Page 36
... The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. Bit 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h. 3.3.2 DID—Device Identification Register (Device 0) Address Offset: Default Value: ...
Page 37
PCICMD—PCI Command Register (Device 0) Address Offset: Default: Access: Size This 16-bit register provides basic control over the 82443BX PCI interface ability to respond to PCI cycles. The PCICMD Register enables and disables the SERR# signal, 82443BX response to ...
Page 38
Register Description 3.3.4 PCISTS—PCI Status Register (Device 0) Address Offset: Default Value: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of a PCI master abort and PCI target abort on the PCI bus. PCISTS also indicates ...
Page 39
RID—Revision Identification Register (Device 0) Address Offset: Default Value: Access: Size: This register contains the revision number of the 82443BX Function #0. These bits are read only and writes to this register have no effect. Bit Revision Identification Number. ...
Page 40
Register Description 3.3.8 MLT—Master Latency Timer Register (Device 0) Address Offset: Default Value: Access: Size: This register controls the amount of time that 82443BX can burst data on the PCI Bus as a PCI master. The MLT[2:0] bits are reserved ...
Page 41
Bit Upper Programmable Base Address bits (R/W). These bits are used to locate the range size selected via lower bits 27:4. 31:28 Default = 0000b Lower “Hardwired”/Programmable Base Address bits. These bits behave as a “hardwired” programmable ...
Page 42
Register Description 3.3.12 SID—Subsystem Identification Register (Device 0) Offset: Default: Access: Size: Bit Subsystem ID (R/WO). This value is used to identify a particular subsystem. The default value is 15:0 00h. This field should be programmed during boot-up. After this ...
Page 43
... Processor mode where external IOAPIC is used, this bit should be set to ‘0’ (default). Setting this bit to ‘0’, enables the WSC# handshake mechanism. 14 Intel Reserved. Host/DRAM Frequency. These bits are used to determine the host and DRAM frequency. Bit 13 is set by an external strapping option at reset. These bits are also used to select the required refresh rate. These bits apply to both SDRAM and EDO, with the exception that the setting ‘ ...
Page 44
Register Description Bit ECC Diagnostic Mode Enable (EDME) (R/W Enable. When this bit is set to 1, the 82443BX will enter ECC Diagnostic test mode and the 82443BX forces the MECC[7:0] lines to 00h for all writes to ...
Page 45
DRAMC—DRAM Control Register (Device 0) Address Offset: Default Value: Access: Size: Bit 7:6 Reserved. Module Mode Configuration (MMCONFIG). This bit is set by an external strapping option. The combination of this bit and the SDRAMPWR bit (SDRAMC register) determine ...
Page 46
Register Description 3.3.16 DRAMT—DRAM Timing Register (Device 0) Address Offset: Default Value: Access: Size: This 8-bit register controls main memory DRAM timings. Refer to the DRAM section for details regarding the DRAM timings programmed in this register. Bit 7:2 Reserved. ...
Page 47
Table 3-2. Attribute Bit Assignment Bits [7, 3] Bits [6, 2] Reserved Reserved example, consider a BIOS that is implemented on the expansion bus. During the initialization process, the BIOS ...
Page 48
Register Description DOS Application Area (00000h–9FFFh) The DOS area is 640 KB and it is further divided into two parts. The 512 KB area 7FFFFh is always mapped to the main memory controlled by the 82443BX, while ...
Page 49
The DRAM array can be configured with single or double-sided DIMMs using 2MX8, 4Mx16, or 8Mx8 parts. The array also supports x4 width DRAM components on registered DIMMs. Each register defines an address range that will cause a particular CS# ...
Page 50
Register Description The following 2 examples describe how the DRB Registers are programmed for cases of single- sided and double-sided DIMMs on a motherboard. Example #1 Single-sided DIMMs Assume a total DRAM are required using single-sided ...
Page 51
MBSC—Memory Buffer Strength Control Register (Device 0) Address Offset: Default Value: Access: Size: This register programs the various DRAM interface signal buffer strengths, based on non-mixed memory configurations of DRAM type (EDO or SDRAM), DRAM density (x8, x16, or ...
Page 52
Register Description Bit MECC [7:0] Buffer Strength Control 2. 4 DIMM FET Configuration: This field sets the buffer strength for the MECC[7:0] path that is connected to DIMM2 and DIMM3 The buffer strength is programmable based upon the SDRAM ECC ...
Page 53
Bit CSA2#/RASA2#, CSB2#/RASB2# Buffer Strength. This field sets the buffer strength for the CSA2#/RASA2#, CSB2#/RASB2# pins (66 MHz & 100 MHz (66 MHz & 100 MHz) CSA1#/RASA1#, CSB1#/RASB1# Buffer Strength. This field sets ...
Page 54
Register Description 3.3.21 SMRAM—System Management RAM Control Register (Device 0) Address Offset: Default Value: Access: Size: The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME ...
Page 55
ESMRAMC—Extended System Management RAM Control Register (Device 0) Address Offset: Default Value: Access: Size: The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is ...
Page 56
Register Description 3.3.23 RPS—SDRAM Row Page Size Register (Device 0) Address Offset: Default Value: Access: Size: This register sets the row page size for SDRAM only. For EDO memory, the page size is fixed at 2 KB. Bit Page Size ...
Page 57
Bit SDRAM Mode Select (SMS). These bits allow the 82443BX to drive various commands to the SDRAMs. These special modes are intended for initialization at power up. SMS 000 001 010 011 7:5 100 101 110 111 Note: BIOS must ...
Page 58
... Reserved. 4 Intel Reserved. DRAM Idle Timer (DIT). This field determines the number of clocks that the DRAM controller will remain in the idle state before precharging all pages. This field is used for both EDO and SDRAM memory systems. 0000 = 0 clocks ...
Page 59
PMCR—Power Management Control Register (Device 0) Address Offset: Default Value: Access Size Bit Power Down SDRAM Enable (PDSE Enable. When PDSE=1, an SDRAM row in idle state will be issued a power down 7 command. The SDRAM ...
Page 60
Register Description 3.3.27 SCRR—Suspend CBR Refresh Rate Register (Device 0) Address Offset: Default Value: Access Size Bit 15:13 Reserved. Suspend CBR refresh Rate Auto Adjust Enable (SRRAEN). SRRAEN bit is cleared to its default during cold reset only ...
Page 61
EAP—Error Address Pointer Register (Device 0) Address Offset: Default Value: Access Size Bit Error Address Pointer (EAP) (RO). This field is used to store the 4 KB block of main memory of which an error (single bit or multi-bit ...
Page 62
Register Description 3.3.29 ERRCMD—Error Command Register (Device 0) Address Offset: Default Value: Access: Size: This 8-bit register controls the 82443BX responses to various system errors. The actual assertion of SERR# is enabled via the PCI Command register. Bit SERR# on ...
Page 63
ERRSTS—Error Status Register (Device 0) Address Offset: Default Value: Access: Size: This 16-bit register is used to report error conditions via the SERR# mechanism. SERR# is generated on a zero to one transition of any of these flags (if ...
Page 64
Register Description 3.3.31 ACAPID—AGP Capability Identifier Register (Device 0) Address Offset: Default Value: Access: Size: This register provides normal identifier for AGP capability. Bit 31:24 Reserved Major AGP Revision Number. This field provides a major revision number of AGP specification ...
Page 65
AGPCMD—AGP Command Register (Device 0) Address Offset: Default Value: Access: Size: This register provides control of the AGP operational parameters. Bit 31:10 Reserved. AGP Side Band Enable. This bit enables the side band addressing mechanism Enable. ...
Page 66
Register Description 3.3.34 AGPCTRL—AGP Control Register (Device 0) Address Offset: Default Value: Access: Size: This register provides for additional control of the AGP interface. Bit 31:16 Reserved. Snoopable Writes In Order With AGP Reads Disable (AGPDCD). When set to 0 ...
Page 67
APSIZE—Aperture Size Register (Device 0) Address Offset: Default Value: Access: Size: This register determines the effective size of the Graphics Aperture used for a particular 82443BX configuration. This register can be updated by the 82443BX-specific BIOS configuration sequence before ...
Page 68
Register Description 3.3.37 MBFS—Memory Buffer Frequency Select Register (Device 0) Address Offset: Default Value: Access: Size: The settings in this register enable the 100 MHz or 66 MHz buffers for each of the following signal groups. Note: The choice of ...
Page 69
Bit CSA7#/CKE3 (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for CSA7#/CKE3 MHz 1 = 100 MHz CSB6#/CKE4 (100 MHz/66 MHz buffer select bit). This bit enables either ...
Page 70
Register Description Bit DQMB1/CASB1# (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for DQMB1/CASB1 MHz 1 = 100 MHz DQMA[7:6,4:2,0]/CASA[7:6,4:2,0]# (100 MHz/66 MHz buffer select bit). This bit ...
Page 71
... QWords between 0–1023 which are permitted to be written to DRAM within one Throttle Monitoring Window while the thermal throttling mechanism is in effect. DRAM Write Throttle Mode. Normal DRAM write monitoring and thermal throttling operation are enabled when bits 2:0 are set to 100. All other combinations are Intel Reserved. 000-011 = Intel Reserved 2:0 ...
Page 72
... Read Throttle Monitoring Window while thermal throttling mechanism is in effect. DRAM Read Throttle Mode. Normal DRAM read monitoring and thermal throttling operation are enabled when bits 2:0 are set to 100. All other combinations are Intel Reserved. 000-011 = Intel Reserved 2:0 ...
Page 73
... Jam Latch control bits had been enabled before the STR was executed. Bit 15:10 Reserved. AGP Jam Latch Strength Select. Bit Enable strong pull-up 9:6 Bit Enable weak pull-up Bit Enable strong pull-down Bit Enable weak pull-down 5:0 Intel Reserved. 82443BX Host Bridge Datasheet F0–F1h 0000h Read/Write 16 bits Description Register Description 3-47 ...
Page 74
Register Description 3.4 PCI-to-PCI Bridge Registers (Device 1) The configuration space for device #1 is controlled by the AGP_DIS bit in the PMCR register. Note: When AGP_DIS = 0, the configuration space for device #1 is enabled, and the registers ...
Page 75
... The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. Bit 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h. 3.4.2 DID1—Device Identification Register (Device 1) Address Offset: Default Value: ...
Page 76
Register Description 3.4.3 PCICMD1—PCI-to-PCI Command Register (Device 1) Address Offset: Default: Access: Size Bit 15:10 Reserved. 9 Fast Back-to-Back: Not Applicable. Hardwired to 0. SERR# Enable (SERRE1). When enabled the SERR# signal driver (common for PCI and AGP) is enabled ...
Page 77
PCISTS1—PCI-to-PCI Status Register (Device 1) Address Offset: Default Value: Access: Size: PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with primary side of the “virtual” PCI-to-PCI bridge embedded within the 82443BX. Bit 15 ...
Page 78
Register Description 3.4.6 SUBC1—Sub-Class Code Register (Device 1) Address Offset: Default Value: Access: Size: This register contains the Sub-Class Code for the 82443BX device #1. This code is 04h indicating a PCI-to-PCI Bridge device. The register is read only. Bit ...
Page 79
HDR1—Header Type Register (Device 1) Offset: Default: Access: Size: This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 Header Type (HEADT). This read only field always returns 01h when ...
Page 80
Register Description 3.4.12 SUBUSN—Subordinate Bus Number Register (Device 1) Offset: Default: Access: Size: This register identifies the subordinate bus (if any) that resides at the level below AGP.This number is programmed by the PCI configuration software to allow mapping of ...
Page 81
IOLIMIT—I/O Limit Address Register (Device 1) Address Offset: Default Value: Access: Size: This register controls the CPU to AGP I/O access routing based on the following formula: IO_BASE=< address =<IO_LIMIT Bit 7:4 I/O Address Limit. Corresponds to A[15:12] of ...
Page 82
Register Description Bit Detected Parity Error (DPE1). Note that the PERRE1 bit does not affect the function of this bit. Also the PERR# is not implemented in the 82443BX 82443BX detected of a parity error in the ...
Page 83
MBASE—Memory Base Address Register (Device 1) Address Offset: Default Value: Access: Size: This register controls the CPU to AGP non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =<MEMORY_LIMIT This register must be initialized by the configuration ...
Page 84
Register Description 3.4.19 PMBASE—Prefetchable Memory Base Address Register (Device 1) Address Offset: Default Value: Access: Size: This register controls the CPU to AGP prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE=< address =<PREFETCHABLE_MEMORY_LIMIT This register must be initialized ...
Page 85
BCTRL—PCI-to-PCI Bridge Control Register (Device 1) Address Offset: Default: Access: Size This register provides extensions to the PCICMD1 register that are specific to PCI-to-PCI bridges. The BCTRL provides additional control for the secondary interface (i.e., AGP) as well as ...
Page 86
...
Page 87
... System Address Map ® A Pentium Pro processor-based system with the Intel addressable memory space and addressable I/O space. (The Pentium bus I/O addressability 3). There is a programmable memory address space under the 1 MB region which is divided into regions which can be individually controlled with programmable attributes such as Disable, Read/Write, Write Only, or Read Only ...
Page 88
... Functional Description 4.1.1 Memory Address Ranges Figure 4-1 provides a detailed 82443BX memory map indicating specific memory regions defined by AGP and supported by the Intel Figure 4-1. Memory System Address Space Window For Non-Prefetchable PCI accesses to AGP (Base=MBASE Reg. (20h); Dev 0) (Size=MLIMIT Reg. (22h); Dev 0) ...
Page 89
Compatibility Area This area is divided into the following address regions: • 0–512 KB DOS Area • 512 KB – 640 KB DOS Area - Optional ISA/PCI Memory • 640KB – 768 KB Video Buffer Area • 768 KB ...
Page 90
Functional Description Monochrome Adapter (MDA) Range (B0000h–B7FFFh) Legacy support requires the ability to have a second graphics controller (monochrome) in the system AGP system, accesses in the normal VGA range are forwarded to the AGP bus. Since the ...
Page 91
... FEC0_0000h (4 GB – 20 MB) to FECF_FFFFh range so that one MTRR can be programmed for the Local and I/O APICs. The I/O APIC(s) usually reside in the I/O Bridge portion of the AGPset stand-alone component(s). For Intel using the PIIX4E, the I/O APIC is supported as a stand-alone component residing on the X-Bus. ...
Page 92
Functional Description 4.1.1.3 AGP Memory Address Range The 82443BX can be programmed to direct memory accesses to the AGP bus interface when addresses are within either of two ranges specified via registers in 82443BX Device #1 configuration space. The first ...
Page 93
Below 1 MB option that supports compatible SMI handlers. • Above 1 MB option that allows new SMI handlers to execute with write-back cacheable SMRAM. • Optional larger write-back cacheable T_SEG area from 128KB to 1MB in size above ...
Page 94
Functional Description Refer to Section 4.8, “Power Management” on page 4-28 Reiteration: • Only un-cacheable SMM regions may overlap PCI or AGP Windows. • SMM regions will not overlap the AGP aperture. • Software (not in SMM) will not access ...
Page 95
Note that the 82443BX Device #1 I/O address range registers defined above are used for all I/O space allocation for any devices requiring such a window on AGP. These devices would include the AGP compliant device and multifunctional AGP compliant ...
Page 96
Functional Description 4.1.5.3 Legacy VGA Ranges The legacy VGA memory range A0000h–BFFFFh is mapped either to PCI or to AGP depending on the programming of the BCTRL configuration register in 82443BX Device #1 configuration space, and the NBXCONF (MDAP bit) ...
Page 97
Table 4-5. Host Bus Transactions Supported By 82443BX Transaction Deferred Reply Reserved Interrupt Acknowledge Special Transactions Reserved Reserved Branch Trace Message Reserved Reserved Reserved I/O Read I/O Write Reserved Memory Read & Invalidate Reserved Memory Code Read Memory Data Read ...
Page 98
Functional Description Table 4-6. Host Responses supported by the 82443BX RS2# RS1 Special Cycles A Special Cycle is defined when REQa[4:0] = 01000 and ...
Page 99
... The Intel 440BX AGPset is optimized for uniprocessor system and also supports the symmetrical multiprocessor configurations two CPUs on the host bus. When configured for dual-processor, the Intel I/O APIC functionality and WSC# signaling mechanism must be enabled. 4.2.3 In-Order Queue Pipelining The 82443BX interface to the CPU bus includes a four deep in-order queue to track pipelined bus transactions ...
Page 100
Functional Description Inte rfac e The 82443BX integrates a main memory DRAM controller that supports a 64-bit or 72-bit (64-bit memory data plus 8 ECC) DRAM array. The DRAM types supported are Synchronous (SDRAM) and ...
Page 101
Single Copy — MD[63:0] — MECC[7:0] — GCKE (for 4 DIMM configuration) — FENA (FET switch control for 4 DIMM configuration) The CS# pins function as RAS# pins in the case of EDO DRAMs. The DQM pins function as ...
Page 102
Functional Description Figure 4-2. Four-DIMM Configuration with FET switches CSA[7:6]#, CSB[7:6]# CSA[5:4]#, CSB[5:4]# CSA[3:2]#, CSB[3:2]# CSA[1:0]#, CSB[1:0]# SRASA# SRASB# SCASA# SCASB# DQMA[1,5] DQMA[7,6,4:2,0] DQMB[1,5] MAA[13:0] MAB[13:11#, 10, 9:0#] MD[63:0] MECC[7:0] DIMM_CLK[3:0] DIMM_CLK[7:4] DIMM_CLK[11:8] DIMM_CLK[15:12] SMB_CLK SMB_DATA 4-16 WEA# WEB# Shift ...
Page 103
Figure 4-3. Three-DIMM SDRAM Configuration CSA[5:4]#, CSB[5:4]# CSA[3:2]#, CSB[3:2]# CSA[1:0]#, CSB[1:0]# DQMA[7,6,4:2,0] MAB[13:11#, 10, 9:0#] DIMM_CLK[3:0] DIMM_CLK[7:4] DIMM_CLK[11:8] 82443BX Host Bridge Datasheet S0/S1,S2/S3 /RAS SRASA# SRASB# /CAS SCASA# SCASB# DQM DQMA[1,5] DQMB[1,5] WE WEA# WEB# MAA[13:0] DQ[63:0] MD[63:0] CB[7:0] MECC[7:0] ...
Page 104
Functional Description Figure 4-4. Three-SODIMMs EDO Configuration 82443BX MAB[13:11#, 10, 9:0#] CASB[5:1]/DQMB[5:1]# RASB[5:0]/CS_B[5:0]# NOTE: 1. These signals are not connected in an EDO configuration. 2. These signals are not used and should be left unconnected. 4-18 RASA[1:0]# RASA[3:2]# RASA[5:4]# CASA[7:0]# ...
Page 105
Figure 4-5. Three-SODIMMs SDRAM Configuration 82443BX MAB[13:11#, 10, 9:0#] CASB[5,1]/DQMB[5:1]# RASB[5:0]/CS_B[5:0]# NOTE: 1. These signals are not used and should be left unconnected. 4.3.1.1 Configuration Mechanism For DIMMS Detection of the type of DRAM installed on the DIMM is supported ...
Page 106
Functional Description DRAM Register Programming The Serial Presence Detect ports are used to determine Refresh Rate, MA and MD Buffer Strength, Row Type (on a row by row basis), EDO Timings, SDRAM Timings, Row Sizes and Row Page Sizes. Table ...
Page 107
This address multiplexing scheme is derived from requirements for each of the row/column organizations for each row size. The SDRAM components used for the options shown in the table are as follows: Option SDRAM Component Type 2 (16MB) 2Mx8 3 ...
Page 108
Functional Description Table 4-11. MA Muxing vs. DRAM Address Split Split Option 1 12x8 11x9 10x10 12x8 Option 2 12x9 13x8* 11x10 12x9 13x8 Option 3 12x10 14x8* 11x11 12x10 13x9 Option 4 14x9* ...
Page 109
... SDRAMC Register Programming Several timing parameters are programmable when using SDRAM in a Intel system. The following table summarizes the programmable parameters. Table 4-12. Programmable SDRAM Timing Parameters Parameter CAS# Latency RAS# to CAS# Delay RAS# Precharge Leadoff CS# assertion The 82443BX can support any combination of CAS# Latency, RAS# to CAS# Delay and RAS# Precharge ...
Page 110
Functional Description 4.3.5 SDRAM Paging Policy Open page arbitration is a paging policy which leaves pages open when handing off ownership of DRAM among masters, and places no restrictions on the number of rows which may have open pages at ...
Page 111
... Data Integrity Support The 82443BX supports ECC (Error Checking and Correcting (Error Checking) data integrity modes on the 64-bit DRAM interface. The Intel® 440BX AGPset does not support the Pentium‚ Pro processor bus ECC protection. This mechanism is defined in the context of the Pentium Pro processor bus specification to support building of mission critical fault-tolerant systems ...
Page 112
Functional Description 4.6.1.4 ECC Generation and Error Detection/Correction and Reporting The 82443BX ECC logic implements the ECC code which is compatible with the algorithm used for the Pentium Pro processor data bus ECC protection. The code is described in the ...
Page 113
... CPU Bus Integrity ® The Intel 440BX AGPset does not support the Pentium Pro processor bus integrity mechanisms. It does not provide support for data protection via ECC, and address/ request signal protection via parity, nor does it support bus protocol error checking or reporting ...
Page 114
... Functional Description 4.7 System Clocking Figure 4-6 shows the clock architecture for a typical Intel ® Figure 4-6. Typical Intel 440BX AGPset System Clocking CK100 BXPCLKx 33 MHz 82443BX 4.8 Power Management This section focuses on the 82443BX power management features only. The PIIX4E datasheet along with this section provide the complete system power management description ...
Page 115
Low-Power Modes Supported by the 82443BX The 82443BX supports a variety of system-wide low power modes using the following functions: • Hardware interface with PIIX4E is used to indicate: — Suspend mode entry. — Resume from suspend. — Whether to ...
Page 116
Functional Description SDRAM Power Down Mode The 82443BX supports SDRAM power down mode. The 82443BX also provides a capability to dynamically enter the SDRAM into low power mode when DRAM rows are idle and resume DRAM activity when transactions request ...
Page 117
Table 4-14. Low Power Mode System Suspend State Powered-On CPU STOP_GRANT / QUICK_START (C2) CPU STOP CLOCK (C3) (DEEP SLEEP) Powered On Suspend (POS, POSCL) Powered On Suspend (POSCL) Suspend to RAM (STR) Suspend -to-Disk (STD) or Powered-Off 82443BX Host ...
Page 118
Functional Description 4.8.2 82443BX Reset The 82443BX reset function is an integral part of the suspend resume functions. The 82443BX supports the normal reset function in a desktop platform, as well as the various power-up reset and resume reset functions ...
Page 119
CPU Reset The CPU reset is generated by the 82443BX in the following case: • CPURST# is always asserted if PCIRST# is asserted. • CPURST# is asserted during resume sequence from POS CRst_En= 1. The 82443BX deasserts CPURST# 1 ...
Page 120
Functional Description Figure 4-8. External Glue Logic Drives CPU Clock Ratio Straps HCLK SUS_DIS strap PCIRST# PCLK p_creset# CRESET# CPU straps 4.8.2.3 82443BX Straps The 82443BX strapping options are latched in the rising edge of PCIRST#. 4.8.3 Suspend Resume 4.8.3.1 ...
Page 121
SDRAM Suspend Refresh When the 82443BX is configured for 3 DIMMs, six CKE signals are provided. When the 82443BX is configured for 4 DIMMs, a single GCKE (global CKE) is provided to allow an external device to correctly drive the ...
Page 122
... SMRAM handlers code to properly execute above 1 MB. Compatible SMRAM (C_SMRAM) This is the traditional SMRAM feature supported in Intel AGPsets. When this function is enabled via C_BASE_SEG[2:0]=010 and G_SMRAME=1 of the SMRAMC register, the 82443BX reserves 000A0000h through 000BFFFFh (A and B segments) of the main memory for use as non- cacheable SMRAM ...
Page 123
Pinout and Pack ag e Information 5.1 82443BX Pinout Figure 5-1 and Figure 5-2 the pinout by ball number. For an alphabetical list of the pinout by signal name refer to 82443BX Host Bridge Datasheet show the ball footprint of ...
Page 124
Pinout and Package Information Figure 5-1. 82443BX Pinout (Top View–left side VSS AD20 B VCC PCLKIN C AD19 REFVCC D AD16 AD18 E IRDY# FRAME# F SERR# PLOCK# G AD13 AD14 H AD8 AD7 J AD5 AD6 ...
Page 125
Figure 5-2. 82443BX Pinout (Top View–right side VSS HD33# HD31# HD43# HD32# HD29# HD37# HD28# HD26# HD34# HD35# HD30# HD38# VSS GTLREFB VCC VSS VCC VSS VCC VSS VSS VSS VCC VSS VSS VCC VSS VCC VSS ...
Page 126
Pinout and Package Information Table 5-1. 82443BX Alphabetical BGA Pin List (Sheet Signal Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 ...
Page 127
Table 5-1. 82443BX Alphabetical BGA Pin List (Sheet Signal Name GIRDY# GPAR GREQ# GSTOP# GTLREFA GTLREFB GTRDY# HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# ...
Page 128
Pinout and Package Information Table 5-1. 82443BX Alphabetical BGA Pin List (Sheet Signal Name MAA12 MAA13 MAB0# MAB1# MAB2# MAB3# MAB4# MAB5# MAB6# MAB7# MAB8# MAB9# MAB10 MAB11# MAB12# MAB13 MD0 MD1 MD2 MD3 MD4 MD5 MD6 ...
Page 129
Table 5-1. 82443BX Alphabetical BGA Pin List (Sheet Signal Name SCASB# SERR# SRASA# SRASB# ST0 ST1 ST2 STOP# BXPWROK SUSTAT# TESTIN# TRDY# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC ...
Page 130
Pinout and Package Information 5.2 Package Dimensions This specification outlines the mechanical dimensions for the 82443BX Host Bridge. The package is a 492 ball grid array (BGA). Figure 5-3. 82443BX BGA Package Dimensions—Top and Side Views Pin A1 corner Pin ...
Page 131
Figure 5-4. 82443BX BGA Package Dimensions—Bottom Views Table 5-2. 82443BX Package Dimensions (492 BGA) Symbol 82443BX Host Bridge Datasheet 24 22 ...
Page 132
... Intel Semicondutores do Brazil LTDA Rua Florida 1703-2 and CJ 22 04565-001-Sao Paulo, SP Brazil Tel: 55-11-5505-2296 FOR MORE INFORMATION To learn more about Intel Corporation visit our site on the World Wide Web at http://www.intel.com/ * Other brands and names are the property of their respective owners. Printed in USA/0498/PSA ...