Z16C3010VEC Zilog, Z16C3010VEC Datasheet - Page 43

• Manufacturer Part Number: Z16C3010VEC
• Description: IC 10MHZ CMOS USC XTEMP 68-PLCC
• Manufacturer: Zilog
• Series: USC®r

Specifications of Z16C3010VEC

• Controller Type: USC Controller
• Interface: DMA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 7mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 7. Z16C30 System Timing
DS007902-0708
No Symbol
1
2
3
4
5
6
7
Notes
1. RxC is RxC or TxC, whichever is supplying the receive clock.
2. TxC is TxC or RxC, whichever is supplying the transmit clock.
TdRxC(REQ) RxC Rise to RxREQ Valid Delay
TdRxC(RxC) TxC Rise to RxC as Receiver Output Valid Delay
TdRxC(INT)
TdTxC(REQ) TxC Fall to TxREQ Valid Delay
TdTxC(TxC)
TdTxC(INT)
TdEXT(INT)
Architecture
The USC internal structure includes two completely independent full-duplex serial chan-
nels, each with two baud rate generators, a digital phase-locked loop for clock recovery,
transmit and receive character counters and a full-duplex DMA interface. The two serial
channels share a common bus interface. The bus interface is designed to provide easy
interface to most microprocessors, whether they employ a multiplexed or nonmultiplexed,
8-bit or16-bit bus structure. Each channel is controlled by a set of thirty 16-bit registers,
nearly all of which are readable and writable. There is one additional 16-bit register in the
bus interface used to configure the nature of the bus interface. The BCR functions are
shown as follows:
Parameter
RxC Rise to INT Valid Delay
RxC Fall to TxC as Transmitter Output Valid
Delay
TxC Fall to INT Valid Delay
CTS, DCD, TxREQ, RxREQ transition to INT
Valid Delay
P R E L I M I N A R Y
Min
Max
100
100
100
100
100
100
100
Product Specification
Electrical Characteristics
Units
ns
ns
ns
ns
ns
ns
ns
Z16C30
Notes
1
1
1
2
2
2
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