ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 96

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
9397 750 13962
Product data
Bit
Symbol
Reset
Access
DAKOLY
R/W
7
0
DRQPOL
Table 83:
Bit
15
14
13
12
11 to 8
7
6
5
4
3
2
1
0
R/W
6
1
DcHardwareConfiguration register: bit description
Symbol
-
EXTPUL
NOLAZY
CLKRUN
CLKDIV[3:0]
DAKOLY
DRQPOL
DAKPOL
EOTPOL
WKUPCS
PWROFF
INTLVL
INTPOL
DAKPOL
R/W
5
0
Rev. 03 — 23 December 2004
EOTPOL
Description
reserved
Logic 1 indicates that an external 1.5 kΩ pull-up resistor is used
on pin D+ and that SoftConnect is not used. Bus reset value:
unchanged.
Logic 1 disables output on pin CLKOUT of the LazyClock
frequency (100 kHz ± 50 %) during ‘suspend’ state. Logic 0
causes pin CLKOUT to switch to LazyClock output after
approximately 2 ms delay, following the setting of bit GOSUSP
in the DcMode register. Bus reset value: unchanged.
Logic 1 indicates that the internal clocks are always running,
even during ‘suspend’ state. Logic 0 switches off the internal
oscillator and PLL, when they are not needed. During ‘suspend’
state this bit must be made logic 0 to meet the suspend current
requirements. The clock is stopped after a delay of
approximately 2 ms, following the setting of bit GOSUSP in the
DcMode register. Bus reset value: unchanged.
This field specifies the clock division factor N, which controls the
clock frequency on output CLKOUT. The output frequency in
MHz is given by 48 / (N + 1). The clock frequency range is
3 MHz to 48 MHz (N = 0 to 15). with a reset value of 12 MHz
(N = 3). The hardware design guarantees no glitches during
frequency change. Bus reset value: unchanged.
Logic 1 selects DACK-only DMA mode. Logic 0 selects
8237 compatible DMA mode. Bus reset value: unchanged.
Selects DREQ2 pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
Selects DACK2 pin signal polarity (0 = active LOW).
Bus reset value: unchanged.
Selects EOT pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
Logic 1 enables remote wake-up via a LOW level on input pin
CS (V
Bus reset value: unchanged.
Logic 1 enables powering-off during ‘suspend’ state. Output
D_SUSPEND pin is configured as a power switch control signal
for external devices (HIGH during ‘suspend’). This value should
always be initialized to logic 1. Bus reset value: unchanged.
Selects the interrupt signalling mode on output pin INT2
(0 = level, 1 = pulsed). In pulsed mode an interrupt produces an
166 ns pulse. See
Bus reset value: unchanged.
Selects INT2 pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
Full-speed USB single-chip host and device controller
R/W
4
0
BUS
must be present for wake-up on CS).
WKUPCS
R/W
3
0
Section 8.6.3
PWROFF
R/W
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
for details.
INTLVL
ISP1161A
R/W
1
0
INTPOL
R/W
95 of 134
0
0