FDC37B727-NS SMSC, FDC37B727-NS Datasheet - Page 57
FDC37B727-NS
Manufacturer Part Number
FDC37B727-NS
Description
IC CTRLR SUPER I/O ENH 128-QFP
Manufacturer
SMSC
Datasheet
1.FDC37B727-NS.pdf
(238 pages)
Specifications of FDC37B727-NS
Controller Type
I/O Controller
Interface
ISA Host
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
30mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1005
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FDC37B727-NS
Manufacturer:
Standard
Quantity:
99
Company:
Part Number:
FDC37B727-NS
Manufacturer:
Microchip Technology
Quantity:
10 000
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Read A Track
This command is similar to the Read Data
command except that the entire data field is read
continuously from each of the sectors of a track.
Immediately after encountering a pulse on the
nINDEX pin, the FDC starts to read all data fields
on the track as continuous blocks of data without
regard to logical sector numbers. If the FDC finds
an error in the ID or DATA CRC check bytes, it
continues to read data from the track and sets the
appropriate error bits at the end of the command.
The FDC compares the ID information read from
each sector with the specified value in the
command and sets the ND flag of Status Register
NC:
LSB:
MT
0
1
Least Significant Bit, the LSB of H is complemented.
No Change, the same value as the one at the beginning of command execution.
HEAD
0
1
0
1
TRANSFERRED TO
FINAL SECTOR
Less than EOT
Less than EOT
Less than EOT
Less than EOT
Equal to EOT
Equal to EOT
Equal to EOT
Equal to EOT
HOST
TABLE 27 - RESULT PHASE
57
C + 1
C + 1
C + 1
NC
NC
NC
NC
NC
1 to a "1" if there is no comparison. Multi-track or
skip operations are not allowed with this
command. The MT and SK bits (bits D7 and D5 of
the first command byte respectively) should always
be set to "0".
This command terminates when the EOT specified
number of sectors has not been read. If the FDC
does not find an ID Address Mark on the diskette
after the second occurrence of a pulse on the IDX
pin, then it sets the IC code in Status Register 0 to
"01" (abnormal termination), sets the MA bit in
Status Register 1 to "1", and terminates the
command.
C
ID INFORMATION AT RESULT PHASE
LSB
LSB
NC
NC
NC
NC
NC
NC
H
R + 1
R + 1
R + 1
R + 1
01
01
01
01
R
NC
NC
NC
NC
NC
NC
NC
NC
N
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