CY7C63310-PXC Cypress Semiconductor Corp, CY7C63310-PXC Datasheet - Page 24

• Manufacturer Part Number: CY7C63310-PXC
• Description: IC USB PERIPHERAL CTRLR 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™IIr

Specifications of CY7C63310-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10-4. OSC Control 0 (OSC_CR0) [0x1E0] [R/W]
Document 38-08035 Rev. *N
Bit [7:6]: Reserved
Bit 5: No Buzz
During sleep (the Sleep bit is set in the CPU_SCR
on periodically to detect any POR and LVD events on the V
the duty
LVD and POR detection circuit to be continuously enabled during sleep. This results in a faster response to an LVD or POR
event during sleep at the expense of a slightly higher than average sleep current.
0 = The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle.
1 = The Sleep Duty Cycle value is overridden. The LVD and POR detection circuit is always enabled.
Note The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep [1:0] bits below.
Bit [4:3]: Sleep Timer [1:0]
Note Sleep intervals are approximate.
Bit [2:0]: CPU Speed [2:0]
The enCoRe II may operate over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero; as a result, the
default CPU speed is one-eighth of the internal 24 MHz, or 3 MHz
Regardless of the CPU Speed bit’s setting, if the actual CPU speed is greater than 12 MHz, the 24 MHz operating requirements
apply. An example of this scenario is a device that is configured to use an external clock, which supplies a frequency of 20 MHz.
If the CPU speed register’s value is 0b011, the CPU clock is at 20 MHz. Therefore, the supply voltage requirements for the device
are the same as if the part were operating at 24 MHz. The operating voltage requirements are not relaxed until the CPU speed
is at 12 MHz or less.
Note Correct USB operations require the CPU clock speed be at least 1.5 MHz or not less than USB clock/8. If the two clocks
have the same source, then the CPU clock divider must not be set to divide by more than 8. If the two clocks have different
sources, the maximum ratio of USB Clock/CPU Clock must never exceed 8 across the full specification range of both clock
sources.
Note This register exists in the second bank of I/O space. This requires setting the XIO bit in the CPU flags register.
Read/Write
CPU Speed
Default
Field
Bit #
[2:0]
000
001
010
100
101
011
110
111
cycle—Table 13-3 on page
3 MHz (Default)
6 MHz
12 MHz
24 MHz
1.5 MHz
750 kHz
187 kHz
Reserved
CPU when Internal
Oscillator is selected
7
–
0
Reserved
6
–
0
33). To facilitate the detection of POR and LVD events, the No Buzz bit is used to force the
Reserved
Clock In/8
Clock In/4
Clock In/2
Clock In/1
Clock In/16
Clock In/32
Clock In/128
External Clock
No Buzz
R/W
5
0
Register—Table 11-1 on page
CC
R/W
pin (the Sleep Duty Cycle bits in the ECO_TR are used to control
4
0
Sleep Timer [1:0]
R/W
3
0
28), the LVD and POR detection circuit is turned
R/W
CY7C63310, CY7C638xx
2
0
CPU Speed [2:0]
R/W
1
0
Page 24 of 86
R/W
0
0
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