SAA7109AE/V1,518 NXP Semiconductors, SAA7109AE/V1,518 Datasheet
SAA7109AE/V1,518
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SAA7109AE/V1,518 Summary of contents
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SAA7108AE; SAA7109AE HD-CODEC Rev. 03 — 6 February 2007 1. General description The SAA7108AE; SAA7109AE is a new multistandard video decoder and encoder chip, offering high quality video input and TV output processing as required by PC-99 specifications. It enables ...
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... NXP Semiconductors The encoder can operate fully independently at its own variable pixel clock, transporting graphics input data, and at the line-locked, single crystal-stable video encoding clock option possible to slave the video PAL/NTSC encoding to the video decoder clock with the encoder FIFO acting as a buffer to decouple the line-locked decoder clock from the crystal-stable encoder clock ...
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... NXP Semiconductors 2.2 Video scaler I Both up and downscaling I Conversion to square pixel format I NTSC to 288 lines (video phone) I Phase accuracy better than I Independent scaling definitions for odd and even fields I Anti-alias filter for horizontal scaling I Provides output as: N Scaled active video N Raw CVBS data for INTERCAST, WAVE-PHORE, POPCON applications or ...
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... NXP Semiconductors I Encoder can be master or slave I Adjustable output levels for the DACs I Programmable horizontal and vertical input synchronization phase I Programmable horizontal sync output phase I Internal Color Bar Generator (CBG) I Optional support of various Vertical Blanking Interval (VBI) data insertion I Macrovision Pay-per-View copy protection system rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option ...
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... NXP Semiconductors 5. Ordering information Table 2. Type number SAA7108AE SAA7109AE 6. Block diagram video input digital video graphics input Fig 1. Simplified block diagram SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Ordering information Package Name Description LBGA156 plastic low profile ball grid array package; 156 balls; ...
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C1, C2, B1, B2, A2, B4, B3, A3, F3, PD11 to H1, H2, H3 INPUT PD0 FORMATTER DECIMATOR PIXCLKI FIFO G4 PIXEL CLOCK PIXCLKO SYNTHESIZER XTALIe Fig 2. ...
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LLC2 RTS0 XCLK XPD [ 7:0 ] LLC RTCO RTS1 XDQ (1) M14 L14 L13 K13 L10 M3 M4 REAL-TIME OUTPUT EXPANSION PORT PIN MAPPING M12 RESd N14 CE CLOCK GENERATION P4 XTOUTd AND P2 POWER-ON CONTROL XTALId P3 XTALOd ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 4. Pin configuration (LBGA156) SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE ball A1 index area SAA7108AE G SAA7109AE Transparent top view Rev. 03 — 6 February 2007 HD-CODEC 001aae257 © NXP B.V. 2007. All rights reserved 208 ...
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A PD7 PD4 TRSTe B PD9 PD8 PD5 PD6 TTX_ TTXRQ_ C PD11 PD10 SRES XCLKO2 D TDOe RESe TMSe V DDIEe E TCKe SCLe HSVGC V SSEe F VSVGC PIXCLKI PD3 V DD(DVO) G FSVGC ...
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... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin A2 PD7 A3 A6 XTALOe A7 A10 V A11 DDAe B1 PD9 B2 B5 TDIe B10 DDAe B13 IPD0 B14 C1 PD11 SSIe C9 V C10 DDAe C13 IPD1 C14 D1 TDOe SSIe D9 V D10 DDAe D13 IPD2 D14 E1 TCKe E2 E11 ...
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... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin P2 XTALId P3 P6 AI24 P7 P10 AI21 P11 7.2 Pin description Table 4. Pin description Symbol Pin PD7 A2 PD4 A3 TRSTe A4 XTALIe A5 XTALOe A6 DUMP SSXe RSET A9 V A10 DDAe HPD0 A11 HPD3 A12 HPD7 A13 PD9 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin PD10 C2 TTX_SRES C3 TTXRQ_XCLKO2 SSIe BLUE_CB_CVBS C6 GREEN_VBS_CVBS C7 RED_CR_C_CVBS DDAe TEST2 C10 HPD2 C11 HPD5 C12 IPD1 C13 IPD5 C14 TDOe D1 RESe D2 TMSe DDIEe V D5 SSIe V D6 DDXe VSM D7 HSM_CSYNC DDAe V D10 DDEd V D11 DDId ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin PD3 DD(DVO) V F11 DDId TVD F12 IGPV F13 IGP0 F14 FSVGC G1 SDAe G2 CBO G3 PIXCLKO G4 V G11 DDEd IGPH G12 IGP1 G13 ITRI G14 PD2 H1 PD1 H2 PD0 SSEd V H11 SSEd ICLK H12 TEST0 H13 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin RTS0 K13 ASCLK K14 XPD5 L1 XPD4 L2 XPD3 DDId XRV SSEd V L7 DDEd V L8 DDXd V L9 DDEd RTS1 L10 V L11 DDId SDAd L12 RTCO L13 LLC2 L14 XPD2 M1 XPD1 M2 XCLK M3 XDQ M4 TMSd M5 TCKd SSAd ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin V N9 SSAd AGND N10 V N11 DDAd V N12 SSAd V N13 SSAd CE N14 XTALId P2 XTALOd P3 XTOUTd SSXd AI24 P6 AI23 P7 AI2D P8 AI22 P9 AI21 P10 AI12 P11 AI1D P12 AI11 P13 [1] Pin type input output supply pull-up. ...
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... NXP Semiconductors Besides the most common 16-bit edge clocking), other C Table 18. A complete 3 bytes a separate gamma corrector, is located in the RGB domain; it can be loaded either through the video input port Pixel Data (PD) or via the I The SAA7108AE; SAA7109AE supports a 32-bit pattern of which can also be loaded through the video input port or via the also possible to encode interlaced video signals such as PC-DVD ...
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... NXP Semiconductors The IC also contains closed caption and extended data services encoding (line 21), and supports teletext insertion for the appropriate bit stream format MHz clock rate (see Figure system into line 20 of every field (525/60 line counting). A number of possibilities are provided for setting different video parameters such as: • ...
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... NXP Semiconductors (1) SCBW = 1. (2) SCBW = 0. Fig 7. Chrominance transfer characteristic (enlargement (dB) (1) CCRS[1:0] = 01. (2) CCRS[1:0] = 10. (3) CCRS[1:0] = 11. (4) CCRS[1:0] = 00. Fig 8. Luminance transfer characteristic (excluding scaler) SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE (dB 0.4 6 (4) 0 ( Rev. 03 — 6 February 2007 mbe735 (1) (2) 0.8 1.2 1 ...
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... NXP Semiconductors (1) CCRS[1:0] = 00. Fig 9. Luminance transfer characteristic (excluding scaler) (enlargement of G (dB) Fig 10. Luminance transfer characteristic in RGB (excluding scaler) SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE (dB Rev. 03 — 6 February 2007 mbe736 ( (MHz HD-CODEC Figure 8) mgb708 14 f (MHz) © NXP B.V. 2007. All rights reserved. ...
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... NXP Semiconductors G (dB) Fig 11. Color difference transfer characteristic in RGB (excluding scaler) 8.1 Reset conditions To activate the reset, a pulse of at least 2 crystal clocks duration is required. During reset (RESe = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC, CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set to 3-state ...
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... NXP Semiconductors 8.2 Input formatter The input formatter converts all accepted PD input data formats, either RGB or Y common internal RGB or Y-C When double-edge clocking is used, the data is internally split into portions PPD1 and PPD2. The clock edge assignment must be set according to the I and EDGE for correct operation ...
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... NXP Semiconductors For each direction, there are 2 registers controlling the position of the cursor, one controls the position of the ‘hot spot’, the other register controls the insertion position. The hot spot is the ‘tip’ of the pointer arrow. It can have any position in the bit map. The actual position registers describe the co-ordinates of the hot spot ...
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... NXP Semiconductors If the SAA7108AE; SAA7109AE input data is in accordance with ‘ITU-R BT.656’ , the scaler enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1. With higher values, upscaling will occur. The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. Small FIFOs rearrange data stream at the scaler output. 8.7 Vertical scaler and anti-fl ...
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... NXP Semiconductors 8.10 Oscillator and Discrete Time Oscillator (DTO) The master clock generation is realized MHz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd harmonic crystal. The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and ...
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... DACs corresponds to approximately 50 IRE also possible to encode closed caption data for 50 Hz field frequencies at 32 times the horizontal line frequency. 8.12.5 Anti-taping (SAA7108AE only) For more information contact your nearest NXP Semiconductors sales office. SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE and Figure 7 ...
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... NXP Semiconductors 8.13 RGB processor This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug. Before Y, C difference signals and 2 times oversampling for luminance and 4 times oversampling for color difference signals is performed. The transfer curves of luminance and color difference components of RGB are illustrated in 8 ...
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... NXP Semiconductors 8.16 Timing generator The synchronization of the SAA7108AE; SAA7109AE is able to operate in two modes; Slave mode and Master mode. In Slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync), VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can be programmed ...
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... NXP Semiconductors 8.17 Pattern generator for HD sync pulses The pattern generator provides appropriate synchronization patterns for the video data path in auxiliary monitor or HDTV mode. It provides maximum flexibility in terms of raster generation for all interlaced and non-interlaced computer graphics or ATSC formats. The sync engine is capable of providing a combination of event-value pairs which can be used to insert certain values in the outgoing data stream at specifi ...
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... NXP Semiconductors To ease the trigger set-up for the sync generation module, a set of registers is provided to set up the screen raster which is defined as width and height. A trigger position can be specifi co-ordinate within the overall dimensions of the screen raster. If the x, y counter matches the specified co-ordinates, a trigger pulse is generated which pre-loads the tables with their initial values ...
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... NXP Semiconductors Table 9. Sequence (hexadecimal Write to subaddress D2h (insertion is done into all three analog output signals Write to subaddress D1h Write to subaddress D3h (no signals are directed to pins HSM_CSYNC and VSM SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Example for setup of the sync tables Comment generate 540 lines of line type index 1 ...
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... NXP Semiconductors Table 9. Sequence (hexadecimal Write to subaddress DCh 0B 2 8.18 I C-bus interface 2 The I C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbit/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write and read, except two read only status bytes ...
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... NXP Semiconductors The second rule is that there has to be data in the buffer FIFO when the encoder enters the active video area. Therefore, the vertical offset in the input path needs bit shorter than the offset of the encoder. The following gives the set of equations required to program the IC for the most common application: A post processor in Master mode with non-interlaced video input data. Some variables are defi ...
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... NXP Semiconductors TPclk TPclk PCL = should be set according to Setting a lower value means that the internal pixel clock is higher and the data get sampled up. The difference may 640 with 320 pixels per line as a rule of thumb. This allows horizontal upscaling by a maximum factor of 2 respectively 4 (this is the parameter RiePclk) ...
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... NXP Semiconductors YINC = YIWGTO YIWGTE When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not be set this case. YIWGTE may go negative. In this event, YINC should be added and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE positive. ...
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... NXP Semiconductors Table 10. Color White Yellow Cyan Green Magenta Red Blue Black [1] Transformation 1.3707 1.7324 Table 11. Data slot control (example for format 0) SLOT Table 12 8-bit non-interlaced RGB/C Pin PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE ...
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... NXP Semiconductors Table 13 5-bit non-interlaced RGB Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Table 14 5-bit non-interlaced RGB Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Table 15 8-bit non-interlaced C Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Table 16. ...
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... NXP Semiconductors Table 16 8-bit interlaced C Pin PD4 PD3 PD2 PD1 PD0 Table 17. 8-bit non-interlaced index color Pin PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 [ don’t care. Table 18 8-bit non-interlaced RGB/C Pin PD11 PD10 PD9 PD8 ...
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... NXP Semiconductors 9. Functional description of digital video decoder part 9.1 Decoder 9.1.1 Analog input processing The SAA7108AE; SAA7109AE offers six analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC; see 9.1.2 Analog control circuits The anti-alias fi ...
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... NXP Semiconductors Signal (white) peak control limits the gain at signal overshoots. The influence of supply voltage variation within the specified range is automatically eliminated by clamping and automatic gain control. The flow charts show more details of the AGC; see Figure 18. Fig 14. Analog line with clamp (HCL) and gain range (HSY) Fig 15 ...
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P6 AI24 P7 AI23 P8 SOURCE AI2D SWITCH CLAMP P9 AI22 CIRCUIT P10 AI21 P11 AI12 CLAMP P12 SOURCE AI1D SWITCH CIRCUIT P13 AI11 MODE CLAMP CONTROL CONTROL MODE[3:0] 9 CVBS/LUM CVBS/CHR Fig 16. Analog input processing using the SAA7108AE; ...
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... NXP Semiconductors Fig 17. Gain flow chart SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE ANALOG INPUT AMPLIFIER ANTI-ALIAS FILTER ADC 1 NO ACTION VBLK 0 510 496 1/F 1/L 1/LLC2 STOP GAIN ACCUMULATOR (18 BITS system variable AGV FGV > GUDL. GUDL = gain update level (adjustable). VBLK = vertical blanking pulse. ...
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... NXP Semiconductors Fig 18. Clamp and gain flow SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE ANALOG INPUT ADC 1 NO BLANKING ACTIVE VBLK <- CLAMP 1 0 HCL 1 0 CLL NO CLAMP CLAMP CLAMP WIPE = white peak level (254). SBOT = sync bottom level (1). CLL = clamp level [60 Y (128 C)]. ...
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CVBS-IN or Y-IN LDEL COMPENSATION YCOMB QUADRATURE MODULATOR CVBS-IN QUADRATURE LOW-PASS 1 or CHR-IN DEMODULATOR DOWNSAMPLING SUBCARRIER GENERATION 2 CHROMINANCE INCREMENT DELAY SUBCARRIER GENERATION 1 HUEC[7:0] RTCO Fig 19. Chrominance and luminance processing Y DELAY LUMINANCE-PEAKING SUBTRACTOR LOW-PASS, CHR Y-DELAY ...
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... NXP Semiconductors 9.1.3.1 Chrominance path The 9-bit CVBS or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0 and 90 phase relationship to the demodulator axis). The frequency is dependent on the chosen color standard. ...
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... NXP Semiconductors • Loop filter chrominance PLL (only active for PAL/NTSC standards) • PAL/SECAM sequence detection, H/2-switch generation The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e ...
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... NXP Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110 (dB (5) LCBW[2:0] = 001. 48 (6) LCBW[2:0] = 011. 51 (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111 Fig 20. Transfer characteristics of the chrominance low-pass at CHBW = 0 SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE (1) (2) (3) (4) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 ...
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... NXP Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110 (dB (5) LCBW[2:0] = 001. 48 (6) LCBW[2:0] = 011. 51 (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111 Fig 21. Transfer characteristics of the chrominance low-pass at CHBW = 1 SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE (1) (2) (3) (4) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 ...
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... NXP Semiconductors 9.1.3.2 Luminance path The rejection of the chrominance components within the 9-bit CVBS or Y input signal is achieved by subtracting the remodulated chrominance signal from the CVBS input. The comb filtered C block. Its characteristic is controlled by LUBW (subaddress 09h, bit 4) to modify the width of the chrominance ‘ ...
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... NXP Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5 (dB (5) LCBW[2:0] = 001. 48 (6) LCBW[2:0] = 011. ...
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... NXP Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5 (dB (5) LCBW[2:0] = 001. 48 (6) LCBW[2:0] = 011. ...
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... NXP Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5 (dB (5) LCBW[2:0] = 001. 48 (6) LCBW[2:0] = 011. ...
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... NXP Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5 (dB (5) LCBW[2:0] = 001. 48 (6) LCBW[2:0] = 011. ...
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... NXP Semiconductors 9 V (dB (1) LUFI[3:0] = 0001. 2 (2) LUFI[3:0] = 0010. (3) LUFI[3:0] = 0011. (4) LUFI[3:0] = 0100. 1 (5) LUFI[3:0] = 0101. (6) LUFI[3:0] = 0110. (7) LUFI[3:0] = 0111. (8) LUFI[3:0] = 0000 (dB (9) LUFI[3:0] = 1000. (10) LUFI[3:0] = 1001. 27 (11) LUFI[3:0] = 1010. (12) LUFI[3:0] = 1011. 30 (13) LUFI[3:0] = 1100. (14) LUFI[3:0] = 1101. 33 (15) LUFI[3:0] = 1110. (16) LUFI[3:0] = 1111. ...
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... NXP Semiconductors 9.1.3.3 Brightness Contrast Saturation (BCS) control and decoder output levels The resulting Y (CVBS) and C following functions: • Chrominance saturation control by DSAT7 to DSAT0 • Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0 • Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0 • ...
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... NXP Semiconductors a. Sources containing 7.5 IRE black level Fig 28. CVBS (raw data) range for scaler input, data slicer and X port output 9.1.4 Synchronization The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz by a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop fi ...
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... NXP Semiconductors Table 19. Clock XTALO LLC LLC2 LLC4 (internal) LLC8 (virtual) LFCO Fig 29. Block diagram of the clock generation circuit 9.1.6 Power-on reset and CE input A missing clock, insufficient digital or analog V the reset sequence; all outputs are forced to 3-state (see RESd is LOW for approximately 128 LLC after the internal reset and can be applied to reset other circuits of the digital TV system ...
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... NXP Semiconductors XTALO LLCINT RESINT LLC RES (internal reset) Fig 30. Power-on control circuit SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE CLOCK PLL LLC 200 s some ms PLL delay POC = power-on control chip enable input. XTALO = crystal oscillator output. LLCINT = internal system clock. RESINT = internal reset. ...
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... NXP Semiconductors 9.2 Decoder output formatter The output interface block of the decoder part contains the ITU 656 formatter for the expansion port data output XPD7 to XPD0 (for a detailed description see and the control circuit for the signals needed for the internal paths to the scaler and data slicer part ...
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LINE NUMBER (1st FIELD) active video 259 260 261 LINE NUMBER (2nd FIELD) active video LCR LINE NUMBER (1st FIELD) 273 274 275 276 LINE NUMBER (2nd FIELD) LCR ...
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... NXP Semiconductors ITU counting 622 623 310 single field counting 309 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 134h VGATE FID ITU counting 309 310 single field counting 310 309 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 134h VGATE FID (1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the fi ...
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... NXP Semiconductors ITU counting 525 single field counting 262 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 101h VGATE FID ITU counting 263 262 single field counting 262 263 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 101h VGATE FID (1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the fi ...
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... NXP Semiconductors Fig 35. Horizontal timing diagram (50/60 Hz) SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE CVBS input processing delay ADC to expansion port: expansion port data output HREF (50 Hz) 720 CREF 50 Hz CREF2 5 HS (50 Hz) programming range 108 (step size: 8/LLC) HREF (60 Hz) 720 ...
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... NXP Semiconductors 9.3 Scaler The High Performance video Scaler (HPS) is based on the system as implemented in previous products (e.g. SAA7140), but with some aspects enhanced. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more flexible video stream timing at the image port, discontinuous transfers and handshake. ...
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... NXP Semiconductors 2. Input from X port: 60 Hz, 720 pixel, 240 lines, 8-bit data at 27 MHz data rate (ITU 656), 2 cycles per pixel; output via port: 16-bit data at 27 MHz clock, 1 cycle per pixel; the maximum HV_zoom is equal to: 0.98 The video scaler receives its input signal from the video decoder or from the expansion port (X port) ...
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... NXP Semiconductors • Vertical offset defined in lines of the video source, parameter YO[11:0] 99h[3:0] 98h[7:0] • Vertical length defined in lines of the video source, parameter YS[11:0] 9Bh[3:0] 9Ah[7:0] • Vertical length defined in number of target lines result of vertical scaling, parameter YD[11:0] 9Fh[3:0] 9Eh[7:0] • ...
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... NXP Semiconductors Table 22. XDV1 92h[ 9.3.1.2 Task handling The task handler controls the switching between the two programming register sets controlled by subaddresses 90h and C0h. A task is enabled via the global control bits TEA[80h[4]] and TEB[80h[5]]. The handler is then triggered by events which can be defined for each register set. ...
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... NXP Semiconductors • Basically the trigger conditions are checked, when a task is activated important to realize, that they are not checked while a task is inactive. So you can not trigger to next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task A STRC[1: YO[11:0] = 310 and task B STRC[1: YO[11:0] = 310 results in an output fi ...
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... NXP Semiconductors Table 23. Examples for field processing Subject Field sequence frame/field Example 1 1/1 1/2 Processed by task A A State of detected 0 1 ITU 656 FID TOGGLE fl Bit 6 of SAV/EAV 0 1 byte Required sequence UP LO conversion at the [8] vertical scaler UP LO [9] Output O O [1] Single task every fi ...
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... NXP Semiconductors 9.3.2.1 Horizontal prescaler (subaddresses A0h to A7h and D0h to D7h) The prescaling function consists of an FIR anti-alias filter stage and an integer prescaler, which creates an adaptive prescale dependent low-pass filter to balance the sharpness and aliasing effects. The FIR prefilter stage implements different low-pass characteristics to reduce the ...
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... NXP Semiconductors Other amplifications have to be normalized by using the following BCS control circuitry. In these cases the prescaler has to be set to an overall gain of sequence of ‘ 1’ (XACL[5: and XC2_1 = 0), XDCG[2:0] must be set to ‘010’, this equals value = lower integer of The use of XACL[5:0] is XPSC[5:0] dependent. XACL[5:0] must be < 2 XACL[5:0] can be used to fi ...
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... NXP Semiconductors (1) PFY[1:0] = 01. (2) PFY[1:0] = 10. (3) PFY[1:0] = 11. Fig 36. Luminance prefilter characteristic (1) PFUV[1:0] = 01. (2) PFUV[1:0] = 10. (3) PFUV[1:0] = 11. Fig 37. Chrominance prefilter characteristic SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE (dB 0.05 0.1 0. (dB 0.025 0.05 0.075 Rev. 03 — 6 February 2007 (1) (2) (3) 0.2 0.25 ...
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... NXP Semiconductors (dB 0. XC2_1 = 0; Zero’s at Fig 38. Examples for prescaler filter characteristics: effect of increasing XACL[5:0] (dB) (1) XC2_1 = 0 and XACL[5: (2) XC2_1 = 1 and XACL[5: (3) XC2_1 = 0 and XACL[5: (4) XC2_1 = 1 and XACL[5: (5) XC2_1 = 0 and XACL[5: (6) XC2_1 = 1 and XACL[5: Fig 39. Examples for prescaler filter characteristics: setting XC2_1 ...
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... NXP Semiconductors Table 25. Example of XACL[5:0] usage Prescale XPSC Recommended values ratio [5:0] For lower bandwidth requirements XACL[5: [1] Resulting FIR function. 9.3.2.2 Horizontal fine scaling (variable phase delay filter; subaddresses A8h to AFh and D8h to DFh) The horizontal fine scaling (VPD) should operate at scaling ratios between (0 ...
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... NXP Semiconductors Luminance and chrominance scale increments (XSCY[12:0] A9h[4:0] A8h[7:0] and XSCC[12:0] ADh[4:0] ACh[7:0]) are defined independently, but must be set relationship in the actual data path implementation. The phase offsets XPHY[7:0] AAh[7:0] and XPHC[7:0] AEh[7:0] can be used to shift the sample phases slightly. ...
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... NXP Semiconductors 9.3.3.2 Vertical scaler (subaddresses B0h to BFh and E0h to EFh) Vertical scaling of any ratio from 64 (theoretical zoom) to The vertical scaling block consists of another line delay, and the vertical filter structure, that can operate in two different modes; Linear Phase Interpolation (LPI) and Accumulation (ACM) mode. These are controlled by YMODE[B4h[0]]: • ...
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... NXP Semiconductors 9.3.3.3 Use of the vertical phase offsets As described in interlaced input sequence. Additionally the interpretation and timing between ITU 656 field ID and real-time detection by means of the state of H-sync at the falling edge of V-sync may result in different field ID interpretation. A vertically scaled interlaced output also gets a larger vertical sampling phase error, if the interlaced input fi ...
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... NXP Semiconductors unscaled input field 1 field 2 scale dependent start offset Fig 40. Basic problem of interlaced vertical scaling (example: downscale field 1 upper B A 1024 ----------- - Offset = = line shift input line shift = input line shift + scale increment = YSCY[15: ---------------------------- - C = scale increment + offset = 0 Fig 41. Derivation of the phase related equations (example: interlace vertical scaling down to ...
Page 78
... NXP Semiconductors Table 26. Input field under processing Upper input lines Upper input lines Lower input lines Lower input lines Table 27. Detected input field upper lines 0 = upper lines 1 = lower lines 1 = lower lines [1] Case 1: OFIDC[90h[6 scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper output lines ...
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... NXP Semiconductors The supported VBI data standards are shown in For lines field, per VBI line standards can be selected (LCR24_[7:0] to LCR2_[7:0] in 57h[7:0] to 41h[7:0]: 23 The definition for line 24 is valid for the rest of the corresponding field, normally no text data (video data) should be selected there (LCR24_[7:0] = FFh) to stop the activity of the VBI data slicer during active video ...
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... NXP Semiconductors 9.5 Image port output formatter (subaddresses 84h to 87h) The output interface consists of a FIFO for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the I port and a decoding and multiplexing unit, which generates the 8-bit or 16-bit wide output data stream and the accompanied reference and supporting information ...
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... NXP Semiconductors Additionally the output formatter limits the amplitude range of the video data (controlled by ILLV[85h[5]]); see Table 29. Output format Y Y only Table 30. Name Table 31. Limit step ILLV[85h[5 9.5.2 Video FIFO (subaddress 86h) The video FIFO at the scaler output contains 32 double words. That corresponds to ...
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... NXP Semiconductors 9.5.3 Text FIFO The data of the internal VBI data slicer is collected in the text FIFO before the transmission over the I port is requested (normally before the video window starts partitioned into two FIFO sections. A complete line is filled into the FIFO before a data transfer is requested. So normally, one line of text data is ready for transfer, while the next text line is collected. Thus sliced text data is delivered as a block of qualifi ...
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... NXP Semiconductors As a further option possible to provide the scaler with an external gating signal on pin ITRDY. Thereby making it possible to hold the data output for a certain time and to get valid output data in bursts of a guaranteed length. The sketched reference signals and events can be mapped to the I port output pins IDQ, IGPH, IGPV, IGP0 and IGP1. For fl ...
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VBI line timing reference code ... SAV SDID DC ... EAV ANC header DID SDID DC ANC header active for DID (subaddress 5Dh) ...
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... NXP Semiconductors Table 34. Bytes stream of the data slicer Nick Comment name DID, subaddress 5Dh = 00h SAV, subaddress 5Dh bit EAV subaddress 5Dh [5] bit 5 = 3Eh subaddress 5Dh [5] bit 5 = 3Fh SDID programmable via subaddress 5Eh [8] DC IDI1 IDI2 CS check sum byte BC valid byte count [1] NEP = inverted EP ...
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... NXP Semiconductors • Audio master Clocks Nominal Increment, ACNI[21:0] 36h[5:0] 35h[7:0] 34h[7:0] according to the equation: See Table 35 Remark: For standard applications the synthesized audio clock AMCLK can be used directly as master clock and as input clock for port AMXCLK (short cut) to generate ASCLK and ALRCLK. For high-end applications it is recommended to use an external analog PLL circuit to enhance the performance of the generated audio clock ...
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... NXP Semiconductors Table 36. AMXCLK (MHz) 12.288 11.2896 8.192 9.6.3 Other control signals Further control signals are available to define reference clock edges and vertical references; see Table 37. Control signal APLL[3Ah[3]] AMVR[3Ah[2]] LRPH[3Ah[1]] SCPH[3Ah[0]] 10. Input/output interfaces and ports of digital video decoder part The SAA7108AE ...
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... NXP Semiconductors 10.1 Analog terminals The SAA7108AE; SAA7109AE has 6 analog inputs AI21 to AI24, AI11 and AI12 (see Table 38) for composite video CVBS or S-video Y/C signal pairs. Additionally, there are two differential reference inputs, which must be connected to ground via a capacitor equivalent to the decoupling capacitors at the 6 inputs. There are no peripheral components required other than these decoupling capacitors and 18 /56 resistors, one set per connected input signal ...
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... NXP Semiconductors Table 39. Symbol AMCLK AMXCLK J12 I ASCLK ALRCLK 10.3 Clock and real-time synchronization signals For the generation of the line-locked video (pixel) clock LLC, and of the frame-locked audio serial bit clock, a crystal accurate frequency reference is required. An oscillator is built-in for fundamental or third harmonic crystals. The supported crystal frequencies are 32.11 MHz or 24.576 MHz (defi ...
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... NXP Semiconductors Table 40. Symbol LLC2 RTCO RTS0 RTS1 10.4 Video expansion port (X port) The expansion port is intended for transporting video streams of image data from other digital video circuits such as MPEG encoder/decoder and video phone codec, to the image port (I port); see The expansion port consists of two groups of signals/pins: • ...
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... NXP Semiconductors Table 41. Symbol Pin XRH XRV XTRI 10.4.1 X port configured as output If the data output is enabled at the expansion port, then the data stream from the decoder is presented. The data format of the 8-bit data bus is dependent on the chosen data type, selectable by the line control registers LCR2 to LCR24; see image port, the sliced data format is not available on the expansion port ...
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... NXP Semiconductors The data type selections by LCR are overruled by setting OFTS2 = 1 (subaddress 13h bit 2). This setting is mainly intended for device production testing. The VPO-bus carries the upper or lower 8 bits of the two ADCs depending on the OFTS[1:0] 13h[1:0] settings; see Table Table 144 Y/C mode is selected, the expansion port carries the multiplexed output signals of both ADCs, and in CVBS mode the output of only one ADC ...
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... NXP Semiconductors Table 44. Line number 261 262 263 264 and 265 0 266 to 282 283 284 285 to 524 525 Table 45. Line number 309 310 311 and 312 0 313 to 335 336 337 to 622 623 624 and 625 1 10.4.2 X port configured as input If the data input mode is selected at the expansion port, then the scaler can select its input data stream from the on-chip video decoder, or from the expansion port (controlled by bit SCSRC[1:0] 91h[5:4]) ...
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... NXP Semiconductors The trigger events on XRH (rising/falling edge) and XRV (rising/falling/both edges) for the scalers acquisition window are defined by XDV[1:0] 92h[5:4] and XDH[92h[2]]. The signal polarity of the qualifier can also be defined (bit XDQ[92h[1]]). Alternatively to a qualifier, the input clock can be applied to a gated clock (clock gated with a data qualifier, controlled by bit XCKS[92h[0]]). In this event, all input data will be qualifi ...
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... NXP Semiconductors • There may be more or less than 720 pixels between SAV and EAV • Data content and number of clock cycles during horizontal and vertical blanking is undefined, and may not be constant • Data stream may be interleaved with not-valid data codes, 00h, but SAV and EAV 4-byte codes are not interleaved with not-valid data codes • ...
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... NXP Semiconductors 10.6 Host port for 16-bit extension of video data I/O (H port) The H port pins HPD can be used for extension of the data I/O paths to 16-bit. The I port has functional priority. If I8_16[93h[6]] is set to logic 1 the output drivers of the H port are enabled depending on the I port enable control. For I8_16 = 0, the HPD output is disabled ...
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... NXP Semiconductors ICLK IDQ IPD [ 7:0 ] IGPH Fig 44. Output timing at the I port for serial 8-bit data at start of a line (ICODE = 0) ICLK IDQ IPD [ 7 IGPH Fig 45. Output timing at the I port for serial 8-bit data at end of a line (ICODE = 1) ICLK IDQ IPD [ 7:0 ] ...
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... NXP Semiconductors ICLK IDQ IPD [ 7 HPD [ 7 SAV IGPH Fig 47. Output timing for 16-bit data output via the I port and the H port with codes (ICODE = 1), timing is like 8-bit output, but packages of 2 bytes per valid cycle IDQ IGPH IGPV Fig 48. Horizontal and vertical gate output timing ...
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Digital video encoder part Table 48. Slave receiver bit allocation map (slave address 88h) Register function Subaddress (hexadecimal) Status byte (read only) 00 Null Common DAC adjust fi DAC adjust coarse 17 G DAC ...
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Table 48. Slave receiver bit allocation map (slave address 88h) Register function Subaddress (hexadecimal) Gain U 5B Gain V 5C Gain U MSB, black level 5D Gain V MSB, blanking level 5E CCR, blanking level VBI 5F Null 60 Standard ...
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Table 48. Slave receiver bit allocation map (slave address 88h) Register function Subaddress (hexadecimal) TTX even request vertical start 78 TTX even request vertical end 79 First active line 7A Last active line 7B TTX mode, MSB vertical 7C Null ...
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Table 48. Slave receiver bit allocation map (slave address 88h) Register function Subaddress (hexadecimal) Weighting factor even 9E Weighting factor MSB 9F Vertical line skip A0 Blank enable for NI-bypass, A1 vertical line skip MSB Border color Y A2 Border ...
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Table 48. Slave receiver bit allocation map (slave address 88h) Register function Subaddress (hexadecimal) Horizontal cursor position F9 Horizontal hot spot, MSB XCP FA Vertical cursor position FB Vertical hot spot, MSB YCP FC Input path control FD Cursor bit ...
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... NXP Semiconductors 2 11.1.1 I C-bus format control registers S 1000 1000 b. to the HD line count array (subaddress D0h) S 1000 1000 c. to cursor bit map (subaddress FEh) S 1000 1000 d. to color look-up table (subaddress FFh) Fig 50 1000 1000 a. to control registers S 1000 1000 b. to cursor bit map or color LUT Fig 51 ...
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... NXP Semiconductors Table 49. Code S Sr 1000 100X A Am SUBADDRESS DATA -------- P RAM ADDRESS [ the read/write control bit logic 0 is order to write logic 1 is order to read. [2] If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed. 11.1.2 Slave receiver Table 50. Legend default value after reset. ...
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... NXP Semiconductors Table 51. Subaddress Bit 17h to 19h 17h 18h 19h Table 52. Bit MSMT[7:0] Table 53. Legend default value after reset. Bit and SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE RGB DAC adjust coarse registers, subaddresses 17h to 19h, bit description Symbol Description must be programmed with logic 0 to ensure compatibility to future enhancements RDACC[4:0] output level coarse adjustment for RED DAC ...
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... NXP Semiconductors Table 54. Legend default value after reset. Subaddress Bit 27h 26h Table 55. Legend default value after reset. Bit 7 and Table 56. Legend default value after reset. Bit SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Wide screen signal registers, subaddresses 26h and 27h, bit description ...
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... NXP Semiconductors Table 57. Legend default value after reset. Subaddress Bit 2Ch 2Bh 2Ah Table 58. Legend default value after reset. Bit Symbol 7 VBSEN 6 CVBSEN1 R/W 5 CVBSEN0 R/W 4 CEN 3 ENCOFF 2 CLK2EN 1 CVBSEN2 R SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Copy generation and CG enable registers, subaddresses 2Ah to 2Ch, bit ...
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... NXP Semiconductors Table 59. Legend default value after reset. Bit and 4 YFIL[1:0] R Table 60. Legend default value after reset. Bit Table 61. Legend default value after reset. Bit SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Input path control register, subaddress 37h, bit description Symbol Access Value Description ...
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... NXP Semiconductors Table 62. Legend default value after reset. Bit Table 63. Legend default value after reset. Bit and 2 - SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Input port control 1 register, subaddress 3Ah, bit description Symbol Access Value Description CBENB R/W 0 data from input ports is encoded 1 color bar with fi ...
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... NXP Semiconductors Table 63. Legend default value after reset. Bit 1 0 Table 64. Subaddress Bit 55h 56h 57h 58h 59h [1] In line 16; LSB first; all other bytes are not relevant for VPS. Table 65. Legend default value after reset. Bit SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE ...
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... NXP Semiconductors Table 66. Gain U and gain U MSB, black level registers, subaddresses 5Bh and 5Dh, bit description Subaddress Bit Symbol 5Bh GAINU[8:0] 5Dh BLCKL[5:0] [1] Variable gain for C signal; input representation in accordance with ‘ITU-R BT.601’ [2] Variable black level; input representation in accordance with ‘ITU-R BT.601’ . ...
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... NXP Semiconductors Table 68. Bit 7 and 6 CCRS[1: Table 69. Legend default value after reset. Bit SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE CCR and blanking level VBI register, subaddress 5Fh, bit description Symbol Access Value Description R/W select cross-color reduction filter in luminance; for overall ...
Page 114
... NXP Semiconductors Table 70. Legend default value after reset recommended value. Bit Symbol 7 RTCE BSTA[6:0] R/W Table 71. Subaddress Bit 66h 65h 64h 63h FSC [1] Examples: a) NTSC PAL B/G: f Table 72. Subaddress Bit 67h 68h 69h 6Ah [1] LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the defi ...
Page 115
... NXP Semiconductors Table 73. Legend default value after reset. Subaddress Bit 6Ch 6Dh [1] Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of all internally generated timing signals. [2] Increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines; ...
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... NXP Semiconductors Table 75. Legend default value after reset. Bit 7 and 6 CCEN[1: Table 76. Subaddress Bit 70h 71h 72h [1] Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed. Table 77. Legend default value after reset. Bit SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Closed caption, teletext enable register, subaddress 6Fh, bit description ...
Page 117
... NXP Semiconductors Table 78. Legend default value after reset and minimum value. Bit Symbol TTXHD[3:0] Table 79. Bit Symbol CSYNCA[4:0] R Table 80. Legend default value after reset. Bit Symbol TTXOVS[7:0] R/W Table 81. Legend default value after reset. Bit Symbol TTXOVE[7:0] R/W Table 82. Legend default value after reset. ...
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... NXP Semiconductors Table 83. Legend default value after reset. Bit Symbol TTXEVE[7:0] R/W Table 84. Bit Symbol FAL[7:0] Table 85. Bit Symbol LAL[7:0] Table 86. Legend default value after reset. Bit Symbol 7 TTX60 6 LAL8 5 TTXO 4 FAL8 3 TTXEVE8 2 TTXOVE8 1 TTXEVS8 0 TTXOVS8 SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE ...
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... NXP Semiconductors Table 87. Subaddress Bit 7Eh 7Fh [1] This bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE. Table 88. Subaddress Bit 81h 82h 83h Table 89. Legend default value after reset. Bit and 2 PCLE[1:0] R/W 1 and 0 PCLI[1:0] SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE ...
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... NXP Semiconductors Table 90. Legend default value after reset nominal value. Bit Table 91. Bit Table 92. Bit Table 93. Bit Table 94. Bit Table 95. Bit 7 and 6 5 and 4 3 and 2 1 and 0 Table 96. Bit SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE FIFO control register, subaddress 85h, bit description ...
Page 121
... NXP Semiconductors Table 97. Bit and 0 YPIX[9:8] Table 98. Bit SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Scaler CTRL, MCB and YPIX register, subaddress 96h, bit description Symbol Access Value Description EFS R/W in Slave mode frame sync signal at pin FSVGC 0 ignored 1 accepted PCBN R/W ...
Page 122
... NXP Semiconductors Table 98. Bit Table 99. Bit Table 100. Input delay, MSB line length register, subaddress 99h, bit description Bit Table 101. Horizontal increment register, subaddress 9Ah, bit description Bit Table 102. Vertical increment register, subaddress 9Bh, bit description Bit SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE ...
Page 123
... NXP Semiconductors Table 103. MSBs vertical and horizontal increment register, subaddress 9Ch, bit description Bit Table 104. Weighting factor odd register, subaddress 9Dh, bit description Bit Table 105. Weighting factor even, subaddress 9Eh, bit description Bit Table 106. Weighting factor MSB register, subaddress 9Fh, bit description ...
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... NXP Semiconductors Table 110. Border color U register, subaddress A3h, bit description Bit Table 111. Border color V register, subaddress A4h, bit description Bit Table 112. Subaddress D0h Data byte HLCA HLC HLT Table 113. Layout of the data bytes in the line count array ...
Page 125
... NXP Semiconductors Table 116. Subaddress D2h Data byte HLPA HPD HPV Table 117. Layout of the data bytes in the line pattern array Byte Table 118. Subaddress D3h Data byte HPVA HPVE HHS HVS Table 119. Layout of the data bytes in the value array ...
Page 126
... NXP Semiconductors Table 121. HD sync trigger state 2 register, subaddress D5h, bit description Bit and 2 HLPPT[1:0] state of the HD pattern pointer after trigger 1 and 0 HLCT[9:8] Table 122. HD sync trigger state 3 register, subaddress D6h, bit description Bit Table 123. HD sync trigger state 4 register, subaddress D7h, bit description ...
Page 127
... NXP Semiconductors Table 126. HD output control register, subaddress DCh, bit description Legend default value after reset. Bit 1 0 Table 127. Cursor color and B registers, subaddresses F0h to F2h, bit description Subaddress Bit F0h F1h F2h Table 128. Cursor color and B registers, subaddresses F3h to F5h, bit description ...
Page 128
... NXP Semiconductors Table 132. Input path control register, subaddress FDh, bit description Bit Symbol 7 LUTOFF R/W 6 CMODE R/W 5 LUTL IF[2:0] 1 MATOFF R/W 0 DFOFF Table 133. Cursor bit map register, subaddress FEh, bit description Data byte CURSA Table 134. Color look-up table register, subaddress FFh, bit description ...
Page 129
... NXP Semiconductors 11.1.3 Slave transmitter Table 135. Status byte register, subaddress 00h, bit description Bit Symbol VER[2: CCRDO 3 CCRDE FSEQ 0 O_E Table 136. Slave transmitter (slave address 89h) Register function Status byte 00h Chip ID FIFO status 80h Table 137. Chip ID register, subaddress 1Ch, bit description ...
Page 130
... NXP Semiconductors Table 138. FIFO status register, subaddress 80h, bit description Bit Symbol Access Value Description IFERR 2 BFERR R 1 OVFL 0 UDFL 11.2 Digital video decoder part 2 11.2.1 I C-bus format S SLAVE ADDRESS W a. Write procedure. S SLAVE ADDRESS W Sr SLAVE ADDRESS R b. Read procedure (combined). ...
Page 131
... NXP Semiconductors Table 139. Description of I Code S Sr SLAVE ADDRESS W SLAVE ADDRESS R ACK-s ACK-m SUBADDRESS DATA P [1] The SAA7108AE; SAA7109AE supports the ‘fast mode’ I 400 kbit/s). [2] If pin RTCO is strapped to V Table 140. Subaddress description and access Subaddress 00h F0h to FFh ...
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Table 141. I C-bus receiver/transmitter overview Register function Subaddress D7 Chip version: register 00h Chip version (read only) 00h Video decoder: registers 01h to 2Fh Front-end part: registers 01h to 05h Increment delay 01h Analog input control 1 02h ...
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Table 141. I C-bus receiver/transmitter overview Register function Subaddress D7 Reserved 1Ah to 1Eh Status byte video decoder (read only, 1Fh OLDSB = 0) Status byte video decoder (read only, 1Fh OLDSB = 1) Reserved 20h to 2Fh Audio ...
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Table 141. I C-bus receiver/transmitter overview Register function Subaddress D7 Slicer status byte 0 (read only) 60h Slicer status byte 1 (read only) 61h Slicer status byte 2 (read only) 62h Reserved 63h to 7Fh X port, I port ...
Page 135
Table 141. I C-bus receiver/transmitter overview Register function Subaddress D7 Vertical input window length 9Ah 9Bh Horizontal output window length 9Ch 9Dh Vertical output window length 9Eh 9Fh FIR filtering and prescaling Horizontal prescaling A0h Accumulation length A1h Prescaler ...
Page 136
Table 141. I C-bus receiver/transmitter overview Register function Subaddress D7 Vertical chrominance phase offset ‘00’ B8h Vertical chrominance phase offset ‘01’ B9h Vertical chrominance phase offset ‘10’ BAh Vertical chrominance phase offset ‘11’ BBh Vertical luminance phase offset ‘00’ ...
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Table 141. I C-bus receiver/transmitter overview Register function Subaddress D7 Luminance brightness control D4h Luminance contrast control D5h Chrominance saturation control D6h Reserved D7h Horizontal phase scaling Horizontal luminance scaling increment D8h D9h Horizontal luminance phase offset DAh Reserved ...
Page 138
... NXP Semiconductors 2 11.2.2 I C-bus details 11.2.2.1 Subaddress 00h Table 142. Chip Version (CV) identification; 00h[7:4]; read only register Function Chip Version (CV) 11.2.2.2 Subaddress 01h The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use recommended position only. ...
Page 139
... NXP Semiconductors Table 144. Analog input control 1 (AICO1); 02h[7:0] Bit [1] To take full advantage of the Y/C modes the I to logic 1 (full luminance bandwidth). AI24 AI23 AI22 AI21 AI12 AI11 Fig 53. Mode 0 CVBS (automatic gain) SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Description ...
Page 140
... NXP Semiconductors AI24 AI23 AI22 AI21 AI12 AI11 Fig 55. Mode 2 CVBS (automatic gain) AI24 AI23 AI22 AI21 AI12 AI11 Fig 57. Mode 4 CVBS (automatic gain) AI24 AI23 AI22 AI21 AI12 AI11 Fig 59. Mode (gain channel 2 AI24 AI23 AI22 AI21 AI12 AI11 Fig 61. Mode (gain channel 2 ...
Page 141
... NXP Semiconductors 11.2.2.4 Subaddress 03h Table 145. Analog input control 2 (AICO2); 03h[6:0] Bit Description 6 HL not reference select HLNRS 0 5 AGC hold during vertical blanking period 4 white peak control off 3 automatic gain control integration 2 gain control fix 1 static gain control channel 2 sign bit ...
Page 142
... NXP Semiconductors 11.2.2.7 Subaddress 06h Table 148. Horizontal sync start; 06h[7:0] Delay time (step size = 8/LLC) 128... 109 (50 Hz) 128... 108 (60 Hz) 108 (50 Hz)... 107 (60 Hz)... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) 11.2.2.8 Subaddress 07h Table 149. Horizontal sync stop; 07h[7:0] ...
Page 143
... NXP Semiconductors Table 150. Sync control; 08h[7:0] Bit 4 and 3 horizontal time 2 1 and 0 vertical noise 11.2.2.10 Subaddress 09h Table 151. Luminance control; 09h[7:0] Bit SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE …continued Description Symbol HTC[1:0] constant selection horizontal PLL HPLL VNOI[1:0] 00 reduction ...
Page 144
... NXP Semiconductors Table 151. Luminance control; 09h[7:0] Bit 11.2.2.11 Subaddress 0Ah Table 152. Luminance brightness control: decoder part; 0Ah[7:0] Offset 255 (bright) 128 (ITU level) 0 (dark) SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE …continued Description Symbol sharpness control, LUFI[3:0] 0001 luminance filter characteristic ...
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... NXP Semiconductors 11.2.2.12 Subaddress 0Bh Table 153. Luminance contrast control: decoder part; 0Bh[7:0] Gain 1.984 (maximum) 1.063 (ITU level) 1.0 0 (luminance off) 1 (inverse luminance) 2 (inverse luminance) 11.2.2.13 Subaddress 0Ch Table 154. Chrominance saturation control: decoder part; 0Ch[7:0] Gain 1.984 (maximum) 1.0 (ITU level) ...
Page 146
... NXP Semiconductors 11.2.2.15 Subaddress 0Eh Table 156. Chrominance control 1; 0Eh[7:0] Bit SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Description Symbol Value clear DTO CDTO 0 1 color standard CSTD[2:0] 000 selection 001 010 011 100 101 110 111 disable DCVF 0 chrominance vertical filter and ...
Page 147
... NXP Semiconductors 11.2.2.16 Subaddress 0Fh Table 157. Chrominance gain control; 0Fh[7:0] Bit Description 7 automatic chrominance gain control chrominance gain value (if ACGC is set to logic 1) 11.2.2.17 Subaddress 10h Table 158. Chrominance control 2; 10h[7:0] Bit 7 and 6 5 and 11.2.2.18 Subaddress 11h Table 159. Mode/delay control; 11h[7:0] ...
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... NXP Semiconductors Table 159. Mode/delay control; 11h[7:0] Bit 11.2.2.19 Subaddress 12h Table 160. RT signal control: RTS0 output; 12h[3:0] The polarity of any signal on RTS0 can be inverted via RTP0[11h[3]]. RTS0 output 3-state Constant LOW CREF (13.5 MHz toggling pulse; see CREF2 (6.75 MHz toggling pulse; see HL ...
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... NXP Semiconductors [1] Function selectable via HLSEL[13h[3]]: a) HLSEL = standard horizontal lock indicator. b) HLSEL = fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. VCRs). Table 161. RT signal control: RTS1 output; 12h[7:4] The polarity of any signal on RTS1 can be inverted via RTP1[11h[6]]. ...
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... NXP Semiconductors 11.2.2.20 Subaddress 13h Table 162. RT/X port output control; 13h[7:0] Bit Description 7 RTCO output enable 6 X port XRH output selection 5 and 4 X port XRV output selection 3 horizontal lock indicator selection XPD7 to XPD0 (port output format selection); see Section 10.4 ...
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... NXP Semiconductors 11.2.2.21 Subaddress 14h Table 163. Analog/ADC/compatibility control; 14h[7:0] Bit Description 7 compatibility bit for SAA7199 6 update time interval for AGC value 5 and 4 analog test select 3 XTOUTd output enable 2 decoder status byte selection; see Table 169 1 and 0 ADC sample clock phase delay 11 ...
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... NXP Semiconductors 11.2.2.23 Subaddress 16h Table 165. VGATE stop; 17h[1] and 16h[7:0] Stop of VGATE pulse (HIGH-to-LOW transition), VGPS = 0; see Field Frame Decimal line value counting 50 Hz 1st 1 312 2nd 314 1st 2 0... 2nd 315 1st 312 ...310 2nd 625 60 Hz 1st ...
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... NXP Semiconductors 11.2.2.26 Subaddress 19h Table 168. Raw data offset control; RAWO[7:0] 19h[7:0]; see Offset 128 LSB 0 LSB +128 LSB 11.2.2.27 Subaddress 1Fh Table 169. Status byte video decoder; 1Fh[7:0]; read only register Bit SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Control bits ...
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... NXP Semiconductors 11.2.3 Programming register audio clock generation See equations in 11.2.3.1 Subaddresses 30h to 32h Table 170. Audio master clock (AMCLK) cycles per field Subaddress 30h 31h 32h 11.2.3.2 Subaddresses 34h to 36h Table 171. Audio master clock (AMCLK) nominal increment Subaddress 34h ...
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... NXP Semiconductors 11.2.4 Programming register VBI data slicer 11.2.4.1 Subaddress 40h Table 175. Slicer control 1; 40h[6:4] Bit 11.2.4.2 Subaddresses 41h to 57h Table 176. Line control register; LCR2 to LCR24 (41h to 57h) See Section 9.2 Name WST625 CC625 VPS WSS WST525 CC525 Test line ...
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... NXP Semiconductors 11.2.4.3 Subaddress 58h Table 177. Programmable framing code; slicer set 58h[7:0]; see Framing code for programmable data types Default value 11.2.4.4 Subaddress 59h Table 178. Horizontal offset for slicer; slicer set 59h and 5Bh Horizontal offset Recommended value 11.2.4.5 Subaddress 5Ah Table 179. Vertical offset for slicer ...
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... NXP Semiconductors 11.2.4.8 Subaddress 5Eh Table 182. Sliced data identification (SDID) code; slicer set 5Eh[5:0] Bit 11.2.4.9 Subaddress 60h Table 183. Slicer status byte 0; 60h[6:2]; read only register Bit 11.2.4.10 Subaddresses 61h and 62h Table 184. Slicer status byte 1; 61h[5:0] and slicer status byte 2; 62h[7:0]; read only ...
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... NXP Semiconductors Table 186. Global control 1; global set 80h[3:0] I port and scaler back-end clock selection ICLK output and back-end clock is line-locked clock LLC from decoder ICLK output and back-end clock is XCLK from X port ICLK output is LLC and back-end clock is LLC2 clock Back-end clock is the ICLK input IDQ pin carries the data qualifi ...
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... NXP Semiconductors Table 189. I port signal definitions; global set 84h[7:6] and 86h[5] I port signal definitions IGP0 is output field ID, as defined by OFIDC[90h[6]] IGP0 is A/B task flag, as defined by CONLH[90h[7]] IGP0 is sliced data flag, framing the sliced VBI data at the I port IGP0 is set to logic 0 (default polarity) IGP0 is the output FIFO almost fi ...
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... NXP Semiconductors Table 192. X port signal definitions text slicer; global set 85h[7:5] X port signal definitions text slicer Video data limited to range 1 to 254 Video data limited to range 8 to 247 Double word byte swap, influences serial output timing [ don’t care. Table 193. I port reference signal polarities; global set 85h[4:0] ...
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... NXP Semiconductors Table 195. I port FIFO flag control and arbitration; global set 86h[3:0] I port FIFO flag control and arbitration FAE FIFO flag almost empty level < 16 double words < 8 double words < 4 double words 0 double words FAF FIFO flag almost full level ...
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... NXP Semiconductors 11.2.5.3 Subaddress 88h Table 198. Power save control; global set 88h[7:4] Power save control DPROG = 0 after reset DPROG = 1 can be used to assign that the device has been programmed; this bit can be monitored in the scalers status byte, bit PRDON; if DPROG was set to ...
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... NXP Semiconductors Table 200. Status information scaler part; 8Fh[7:0]; read only register Bit [1] Status information is unsynchronized and shows the actual status at the time of I 11.2.5.5 Subaddresses 90h and C0h Table 201. Task handling control; register set A [90h[7:6]] and B [C0h[7:6]] Event handler control Output fi ...
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... NXP Semiconductors 11.2.5.6 Subaddresses 91h to 93h Table 204. X port formats and configuration; register set A [91h[7:3]] and B [C1h[7:3]] Scaler input format and configuration source selection Only if XRQT[83h[2 scaler input source reacts on SAA7108AE; SAA7109AE request Scaler input source is a continuous data stream, which cannot be interrupted (must be logic 1, if SAA7108AE ...
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... NXP Semiconductors Table 206. X port input reference signal definitions; register set A [92h[7:4]] and X port input reference signal definitions Rising edge of XRV input and decoder V123 is vertical reference Falling edge of XRV input and decoder V123 is vertical reference XRV is a V-sync or V gate signal ...
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... NXP Semiconductors Table 208. I port output format and configuration; register set A [93h[7:5]] and I port output format and configuration All lines will be output Skip the number of leading Y only lines, as defined by FOI1 and FOI0 Double words are transferred byte wise, see subaddress 85h bits ...
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... NXP Semiconductors 11.2.5.7 Subaddresses 94h to 9Bh Table 210. Horizontal input window start; register set A [94h[7:0]; 95h[3:0]] and B [C4h[7:0]; C5h[3:0]] Horizontal input acquisition window definition offset in [1] X (horizontal) direction A minimum of 2 should be kept, due to a line counting mismatch Odd offsets are changing the ...
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... NXP Semiconductors Table 213. Vertical input window length; register set A [9Ah[7:0]; 9Bh[3:0]] and B [CAh[7:0]; CBh[3:0]] Vertical input acquisition window definition input window length in Y (vertical) [1] direction No input lines 1 input line Maximum possible number of input lines = 4095 [1] For trigger condition: STRC[1:0] 90h[1: > (number of input lines per field conditions: YS > ...
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... NXP Semiconductors 11.2.5.9 Subaddresses A0h to A2h Table 216. Horizontal prescaling; register set A [A0h[5:0]] and B [D0h[5:0]] Horizontal integer prescaling ratio (XPSC) Not allowed Downscale = 1 Downscale = ... Downscale = Table 217. Accumulation length; register set A [A1h[5:0]] and B [D1h[5:0]] Horizontal prescaler accumulation sequence length (XACL) Accumulation length = 1 Accumulation length = 2 ...
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... NXP Semiconductors Table 219. Prescaler DC gain and FIR prefilter control; register set A [A2h[3:0]] and Prescaler DC gain Prescaler output is renormalized by gain factor = Weighting of all accumulated samples is factor ‘1’; e.g. XACL = 4 Weighting of samples inside sequence is factor ‘2’; e.g. XACL = 4 [ don’ ...
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... NXP Semiconductors 11.2.5.11 Subaddresses A8h to AEh Table 223. Horizontal luminance scaling increment; register set A [A8h[7:0]; A9h[7:0]] and Horizontal luminance scaling increment Scale = zoom Scale = defined by data path structure Scale = Scale = 1, equals 1024 Scale = Scale = [1] Bits XSCY[15:13] are reserved and are set to logic 0. ...
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... NXP Semiconductors 11.2.5.12 Subaddresses B0h to BFh Table 227. Vertical luminance scaling increment; register set A [B0h[7:0]; B1h[7:0]] and Vertical luminance scaling increment Scale = Scale = Scale = 1, equals 1024 Scale = Scale = Table 228. Vertical chrominance scaling increment; register set A [B2h[7:0]; B3h[7:0]] and Vertical chrominance scaling ...
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... NXP Semiconductors Table 231. Vertical luminance phase offset ‘00’; register set A [BCh[7:0]] and B [ECh[7:0]] Vertical luminance phase Control bits offset YPY07 Offset = Offset = = 1 line 0 32 255 Offset = lines 1 32 12. Programming start setup of digital video decoder part 12.1 Decoder part The given values force the following behavior of the SAA7108AE; SAA7109AE decoder part: • ...
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... NXP Semiconductors Table 232. Decoder part start setup values for the three main standards Subaddress Register function (hexadecimal) 0F chrominance gain control 10 chrominance control 2 11 mode/delay control 12 RT signal control 13 RT/X port output control 14 analog/ADC/compatibility control 15 VGATE start, FID change 16 VGATE stop ...
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... NXP Semiconductors Table 233. Audio clock part setup values Subaddress Register function (hexadecimal) 30 audio master clock cycles per field; bits audio master clock cycles per field; bits audio master clock cycles per field; bits 17 and 16 33 reserved 34 audio master clock nominal increment ...
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... NXP Semiconductors Table 234. Data slicer start setup values Subaddress Register function (hexadecimal) 5B field offset and MSBs for horizontal and vertical offset 5C reserved 5D header and data identification code control 5E sliced data identification code 5F reserved 60 slicer status byte 0 61 slicer status byte 1 ...
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... NXP Semiconductors 12.4.1 Trigger condition For trigger condition STRC[1:0] 90h[1:0] not equal ‘00’. If the value of (YO + YS) is greater than or equal to 262 (NTSC), respectively 312 (PAL) the output field rate is reduced to 30 Hz, respectively 25 Hz. Horizontal and vertical offsets (XO and YO) have to be used to adjust the displayed video in the display window ...
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... NXP Semiconductors Table 236. Scaler and interface configuration example 2 I C-bus address (hex) Global settings Task A: scaler input configuration and output format settings Input and output window definition Prefiltering and prescaling SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Main functionality task enable, IDQ and back-end clock defi ...
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... NXP Semiconductors Table 236. Scaler and interface configuration example 2 I C-bus address (hex Horizontal phase scaling Vertical scaling vertical phase offsets SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Main functionality scaler brightness control scaler contrast control scaler saturation control horizontal scaling increment for ...
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... NXP Semiconductors 13. Limiting values Table 237. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected together and grounded (0 V); all supply pins connected together. Symbol Parameter V DDD V DDA V i(A) V i( stg T amb V esd [1] Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < V [2] Class 2 according to JESD22-A114D ...
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... NXP Semiconductors 15. Characteristics Table 239. Characteristics of the digital video encoder part (typical values measured at T amb Symbol Parameter Supplies V analog supply voltage DDA V digital supply voltage DDIe V digital supply voltage DD(DVO) (DVO) I analog supply current DDA I digital supply current DDD Inputs ...
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... NXP Semiconductors Table 239. Characteristics of the digital video encoder part (typical values measured at T amb Symbol Parameter 2 I C-bus; pins SDAe and SCLe V LOW-level input voltage IL V HIGH-level input IH voltage I input current i V LOW-level output OL voltage (pin SDAe) I output current o Clock timing; pins PIXCLKI and PIXCLKO ...
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... NXP Semiconductors Table 239. Characteristics of the digital video encoder part (typical values measured at T amb Symbol Parameter t output hold time o(h) t output delay time o(d) CVBS and RGB outputs V output voltage CVBS o(CVBS)(p-p) (peak-to-peak value) V output voltage VBS o(VBS)(p-p) ...
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... NXP Semiconductors Table 240. Characteristics of the digital video decoder part DDD DDA levels refer to drawings and conditions illustrated in Symbol Parameter Supplies V digital supply voltage DDD I digital supply current DDD P power dissipation digital D part V analog supply voltage DDA I analog supply current ...
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... NXP Semiconductors Table 240. Characteristics of the digital video decoder part DDD DDA levels refer to drawings and conditions illustrated in Symbol Parameter Digital inputs V LOW-level input voltage IL(SDAd,SCLd) pins SDAd and SCLd V HIGH-level input voltage IH(SDAd,SCLd) pins SDAd and SCLd V LOW-level CMOS input ...
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... NXP Semiconductors Table 240. Characteristics of the digital video decoder part DDD DDA levels refer to drawings and conditions illustrated in Symbol Parameter Subcarrier PLL f nominal subcarrier sc(nom) frequency f lock-in range sc Crystal oscillator for 32.11 MHz f nominal crystal frequency 3rd harmonic xtal(nom) ...
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... NXP Semiconductors Table 240. Characteristics of the digital video decoder part DDD DDA levels refer to drawings and conditions illustrated in Symbol Parameter Clock output timing C output load capacitance L T cycle time cy duty factor for t /t XCLKH XCLKL t rise time r t fall time ...
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... NXP Semiconductors 16. Timing 16.1 Digital video encoder part PIXCLKO t d(CLKD) PIXCLKI PDn any output Fig 63. Input/output timing specification HSVGC CBO PD Fig 64. Horizontal input timing SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE T PIXCLK t HIGH HD;DAT HD;DAT t SU;DAT t o(d) t o(h) XOFS IDEL XPIX HLEN Rev. 03 — ...
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... NXP Semiconductors HSVGC VSVGC Fig 65. Vertical input timing 16.1.1 Teletext timing Time t FD VBS output signal, such that it appears at t after the leading edge of the horizontal synchronization pulse. Time t PD TTXRQ_XCLKO2 in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH state at output pin TTXRQ_XCLKO2, a new teletext bit must be provided by the source ...
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... NXP Semiconductors CVBS/Y t TTX text bit #: 1 TTX_SRES t PD TTXRQ_XCLKO2 Fig 66. Teletext timing SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE Rev. 03 — 6 February 2007 t i(TTXW © NXP B.V. 2007. All rights reserved. HD-CODEC 24 mhb891 190 of 208 ...
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... NXP Semiconductors 16.2 Digital video decoder part clock input XCLK t SU;DAT data and control inputs (X port) input XDQ data and control outputs X port, I port clock outputs LLC, LLC2, XCLK, ICLK and ICLK input Fig 67. Data input/output timing diagram (X port, RT port and I port) ...
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... NXP Semiconductors 17. Application information V (XL8 (IL11 (IL4 (IJ11 (IJ4 (IF11 (ID11 (EL9 (EL7 (EG11 (ED10 (AM8 (AM9 (AN11) DD 32.11 MHz 24.576 MHz V DGND DDP JP43 fXTAL R12 AUDIO2 4.7 k 'strapping C-BUS_Adr:40h/42h V DGND DDP JP44 R13 RCON0 4.7 k 'strapping' C100 R19 AI24 ...
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... NXP Semiconductors AGND Fig 69. Decoupling circuit supply voltages SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE C55 C53 C54 C52 C48 C51 100 100 100 100 100 100 L36 ferrite open AGND DGND Rev. 03 — 6 February 2007 C49 C50 C60 C56 C59 C57 ...
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... NXP Semiconductors 3.3 V digital AGND 0.1 F 0.1 F DGND DGND V V DD(DVO) DDIEe F4 D4 digital SAA7108AE inputs SAA7109AE and outputs C5 SSIe SSEe DGND DGND AGND Fig 70. Application circuit (encoder part) Fig 71. FLTR0, FLTR1 and FLTR2 as shown in SAA7108AE_SAA7109AE_3 Product data sheet SAA7108AE; SAA7109AE 3 ...
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... NXP Semiconductors SAA7108AE SAA7109AE P2 P3 XTALId XTALOd 32.11 MHz 4 With 3rd harmonic quartz. Crystal load = 8 pF. SAA7108AE SAA7109AE P2 P3 XTALId XTALOd 24.576 MHz 4 With 3rd harmonic quartz. Crystal load = 8 pF. SAA7108AE SAA7109AE P2 P3 XTALId 32.11 MHz or 24.576 MHz n.c. clock g. With direct clock. ...
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... NXP Semiconductors a. With 3rd harmonic quartz. c. With direct clock. Fig 73. Oscillator application for encoder part 17.1 Reconstruction filter Figure 71 its cut-off frequency of 6 MHz not suitable for HDTV applications. 17.2 Analog output voltages The analog output voltages are dependent on the total load (typical value 37.5 ), the digital gain parameters and the I settings) ...
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... NXP Semiconductors The digital output signals in front of the DACs under nominal (nominal here stands for the settings given in conditions occupy different conversion ranges, as indicated in bar signal. By setting the reference currents of the DACs as shown in amplitudes can be achieved for all signal combinations assumed that in subaddress 16h, parameter DACF = 0000b, that means the fi ...
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... NXP Semiconductors 18. Test information 18.1 Boundary scan test The SAA7108AE; SAA7109AE has built-in logic and 2 times 5 dedicated pins to support boundary scan testing, separately for the encoder and decoder part, which allows board testing without special hardware (nails). The SAA7108AE; SAA7109AE follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture” ...
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... NXP Semiconductors 18.1.2 Device identification codes A device identification register is specified in “IEEE Std. 1149.1b-1994” 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and to determine the version number of the ICs during fi ...
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... NXP Semiconductors 19. Package outline LBGA156: plastic low profile ball grid array package; 156 balls; body 1.05 mm ball A1 index area ball index area 2 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.45 1.20 0.55 mm 1.65 0.35 0.95 0.45 OUTLINE VERSION IEC SOT700 Fig 75. Package outline SOT700-1 (LBGA156) ...