ADV202BBC-135 Analog Devices Inc, ADV202BBC-135 Datasheet - Page 11

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ADV202BBC-135

Manufacturer Part Number
ADV202BBC-135
Description
IC CODEC VIDEO 135MHZ 144CSPBGA
Manufacturer
Analog Devices Inc
Type
JPEG2000 Video Codecr
Datasheet

Specifications of ADV202BBC-135

Resolution (bits)
16 b
Sigma Delta
No
Voltage - Supply, Analog
1.5V, 3.3V
Voltage - Supply, Digital
1.5V, 3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-CSPBGA
Operating Supply Voltage (typ)
1.5V
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Package Type
CSPBGA
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
DREQ / DACK DMA MODE—SINGLE FIFO READ OPERATION
Table 7.
Parameter
DREQ
t
t
t
t
DACK
DACK
t
RDFSRQ
t
1
2
DREQ
RD SU
RD
HD
RD HD
DREQ RTN
Applies to assigned DMA channel, if EDMOD0 or EDMOD1[14:11] is programmed to a nonzero value.
For a definition of JCLK, see the PLL section.
PULSE
LO
HI
HDATA
HDATA
DREQ
DACK
DREQ
DACK
RD
RD
Description
DREQ Pulse Width
DACK Assert to Subsequent DREQ Delay
RD to DACK Setup
DACK to Data Valid
Data Hold
DACK Assert Pulse Width
DACK Deassert Pulse Width
RD Hold After DACK Deassert
RD Assert to FSRQ Deassert (FIFO Empty)
DACK to DREQ Deassert (DR × PULS = 0)
DREQ
t
t
Figure 10. Single Read for DREQ / DACK DMA Mode for Assigned DMA Channel
Figure 9. Single Read for DREQ / DACK DMA Mode for Assigned DMA Channel
RDSU
RDSU
1
PULSE
(EDMOD0/EDMOD1[14:11] Not Programmed to a Value of 0000)
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
DACK
DACK
t
t
RD
RD
t
LO
t
LO
DREQ
DREQRTN
0
0
DACK
DACK
t
t
HD
HD
HI
HI
Rev. C | Page 11 of 40
1
1
Min
1
2.5
0
2.5
1.5
2
2
0
1.5
2.5
2
2
Typ
t
t
RDHD
RDHD
Max
15
3.5 × JCLK + 7.5 ns
11
2.5 × JCLK + 7.5 ns
3.5 × JCLK + 7.5 ns
Unit
JCLK cycles
JCLK cycles
ns
ns
ns
JCLK cycles
JCLK cycles
ns
JCLK cycles
JCLK cycles
ADV202
2

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