AD1819BJST-REEL Analog Devices Inc, AD1819BJST-REEL Datasheet

Page 1

AC’97 FEATURES Fully Compliant AC’97 Analog I/O Component 48-Terminal LQFP Package Multibit Converter Architecture for Improved S/N Ratio >90 dB 16-Bit Stereo Full-Duplex Codec Four Analog Line-Level Stereo Inputs for Connection from LINE, CD, VIDEO, and AUX Two Analog ...

Page 2

AD1819B PRODUCT OVERVIEW The AD1819B SoundPort Codec is designed to meet all require- ments of the Audio Codec ’97, Component Specification, Revision 1.03, © 1996, Intel Corporation, found at www.Intel.com. In addition, the AD1819B supports multiple codec configurations (up to ...

Page 3

SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature 25 Digital Supply (V ) 5.0 DD Analog Supply (V ) 5.0 CC Sample Rate ( Input Signal 1008 Analog Output Passband kHz V (AC-Link) ...

Page 4

AD1819B–SPECIFICATIONS ANALOG-TO-DIGITAL CONVERTERS Parameter Resolution Total Harmonic Distortion (THD) Dynamic Range (–60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) ...

Page 5

STATIC DIGITAL SPECIFICATIONS Parameter High-Level Input Voltage (V ): Digital Inputs IH Low-Level Input Voltage ( High-Level Output Voltage ( Low-Level Output Voltage ( Input Leakage Current Output Leakage Current ...

Page 6

AD1819B TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE) Parameter RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Start-Up Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Start-Up Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter* BIT_CLK ...

Page 7

... REV. 0 BIT_CLK SDATA_OUT SDATA_IN Figure 6. AC-Link, Link Low Power Mode Timing t FALLCLK t FALLSYNC SDATA_IN, BIT_CLK t FALLDIN t FALLDOUT Max Units Model 6.0 V AD1819BJST – +85 C 48-Terminal LQFP ST-48 6.0 V 10.0 mA *ST = Thin Quad Flatpack 0 ENVIRONMENTAL CONDITIONS Ambient Temperature Rating + +150 C ...

Page 8

AD1819B SDATA_OUT Digital I/O Pin Name LQFP I/O XTL_IN 2 I XTL_OUT 3 O SDATA_OUT 5 I BIT_CLK 6 O/I* SDATA_IN 8 O SYNC 10 I RESET 11 I *Input if the AD1819B is configured as Slave 1 or Slave ...

Page 9

Analog I/O These signals connect the AD1819B component to analog sources and sinks, including microphones and speakers. Pin Name LQFP I/O PC_BEEP 12 I PHONE_IN 13 I AUX_L 14 I AUX_R 15 I VIDEO_L 16 I VIDEO_R 17 I CD_L ...

Page 10

AD1819B MIC1 0dB/20dB MS M20 0x0E MIC2 0x20 LINE_IN AUX CD VIDEO PHONE_IN GA 0x0C PHV M 0x0C PHM M 0x02 A 0x02 LINE_OUT_L LMV MM M 0x06 A 0x06 0 MONO_OUT 1 MMM MMV MIX 0x20 A 0x02 M ...

Page 11

Indexed Control Registers ...

Page 12

AD1819B Reset (Index 00h Note: Writing any value to this ...

Page 13

MMM Beep (Index 0Ah ...

Page 14

AD1819B CD Volume (Index 12h RCV [4:0] Right CD ...

Page 15

Record Select Control (Index 1Ah [2:0] ...

Page 16

AD1819B MIX Mono Output Select Mix Mic. 3D Phat Stereo Enhancement Phat Stereo is off Phat Stereo is on. POP PCM Output Path. The POP bit controls the optional PCM out 3D ...

Page 17

Serial Configuration (Index 74h ...

Page 18

AD1819B Sample Rate 0 (Index 78h ...

Page 19

The AC-Link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A “1” given bit position of Slot 0 indicates ...

Page 20

AD1819B SDATA_OUT’s composite stream is MSB justified (MSB first) with all nonvalid slots’ bit positions stuffed with 0s by the AC’97 controller. The AD1819B ignores invalid slots. In the event that there are less than 20 valid bits within an ...

Page 21

Slot 5–Slot 8: Multicodec Communication • Slot 5 Slave 1 PCM Playback Left Channel • Slot 6 Slave 1 PCM Playback Right Channel • Slot 7 Slave 2 PCM Playback Left Channel • Slot 8 Slave 2 PCM Playback Right ...

Page 22

AD1819B TAG Phase Bit Assignments: Bit (15) Codec Ready Bit (14) Slot 1 Valid Bit (13) Slot 2 Valid Bit (12) Slot 3 Valid/ADC Left Data Is Valid on Slot 3 Bit (11) Slot 4 Valid/ADC Right Data Is Valid ...

Page 23

SDATA_OUT BIT_CLK and SDATA_IN are transitioned low immediately following the decode of the write to the Power-Down Register (26h) with PR4. When the AC’97 controller driver is at the point where it is ready to program the AC-Link into its ...

Page 24

AD1819B MULTIPLE CODE CONFIGURATION Setting Up Multiple Codecs The AD1819B may be used with up to two additional AD1819 or AD1819B codecs. In order to configure the codecs as Mas- ter, Slave 1 or Slave 2, refer to the following ...

Page 25

APPLICATIONS CIRCUITS The AD1819B has been designed to require a minimum amount of external circuitry. The recommended applications circuits are shown in Figures 15–18. Reference designs for the AD1819B are available and may be obtained by contacting your local Analog ...

Page 26

AD1819B RESET SDATA_OUT SDATA_IN SYNC AD1819B BIT_CLK MASTER CS0 CS1 CHAIN_IN CHAIN_CLK XTAL_OUT XTAL_IN 24.576MHz 22pF 22pF NP0 NP0 RESET SDATA_OUT SDATA_IN SYNC AD1819B BIT_CLK SLAVE 1 CS0 CS1 CHAIN_IN CHAIN_CLK XTAL_OUT XTAL_IN RESET SDATA_OUT SDATA_IN SYNC AD1819B BIT_CLK SLAVE ...

Page 27

RESET SDATA_OUT SDATA_IN SYNC AD1819B BIT_CLK MASTER CS0 CS1 CHAIN_IN CHAIN_CLK XTAL_OUT XTAL_IN 24.576MHz 22pF 22pF NP0 NP0 RESET SDATA_OUT SDATA_IN SYNC AD1819B BIT_CLK SLAVE 1 CS0 CS1 CHAIN_IN CHAIN_CLK XTAL_OUT XTAL_IN MIC INPUT 10mV RMS NOTES: *MAY NEED TO ...

Page 28

AD1819B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Terminal LQFP (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC 0.030 (0.75) 0.057 (1.45) 0.276 (7.0) BSC 0.030 (0.75) 0.018 (0.45) 0.053 (1.35) 0.018 (0.45 SEATING PLANE TOP VIEW (PINS ...