EMC1001-AFZQ-TR SMSC, EMC1001-AFZQ-TR Datasheet - Page 7

• Manufacturer Part Number: EMC1001-AFZQ-TR
• Description: Board Mount Temperature Sensors SMBus Temp Snsr
• Manufacturer: SMSC

Specifications of EMC1001-AFZQ-TR

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.5°C SMBus Temperature Sensor in Miniature SOT-23
Datasheet
Chapter 3 System Management Bus Interface Protocol
SMSC EMC1001
3.1
3.2
3.3
START
SM CLK
SM DA TA
1
FIELD:
START
Bits:
1
SLAVE ADDRESS
The Send Byte protocol is used to set the Internal Address Register to the correct Address. The Send
Byte can be followed by the Receive Byte protocol described below in order to read data from the
register. The send byte protocol cannot be used to write data - if data is to be written to a register then
the write byte protocol must be used as described in subsection above. The send byte protocol is shown
in
7
A host controller, such as an SMSC I/O controller, communicates with the EMC1001 via the two wire
serial interface named SMBus. The SMBus interface is used to read and write registers in the
EMC1001, which is a slave-only device. A detailed timing diagram is shown in
The EMC1001 implements a subset of the SMBus specification and supports Write Byte, Read Byte,
Send Byte, Receive Byte, and Alert Response Address protocols. as shown. In the tables that describe
the protocol, the “gray” columns indicate that the slave is driving the bus.
The Write Byte protocol is used to write one byte of data to the registers as shown below:
The Read Byte protocol is used to read one byte of data from the registers as shown below:
Write Byte
Read Byte
Send Byte
Table
P
START
SLAVE ADDRESS
T
1
B U F
3.3.
WR
7
1
S
Figure 3.1 System Management Bus Timing Diagram
ACK
T
T
S - S tart C ondition
SLAVE ADDR
H D :S TA
LO W
1
COMMAND
7
T
Table 3.1 SMBus Write Byte Protocol
Table 3.2 SMBus Read Byte Protocol
Table 3.3 SMBus Send Byte Protocol
R
WR
1
8
T
H IG H
T
H D :D A T
ACK
ACK
DATASHEET
1
1
T
S U :D AT
WR
1
START
T
F
1
7
COMMAND
SLAVE ADDRESS
8
ACK
1
7
S
ACK
1
REG. ADDR
T
SU :S TA
RD
1
T
8
H D :STA
DATA
ACK
1
8
P - Stop Condition
DATA
Figure
8
Revision 1.6 (01-29-07)
ACK
ACK
1
1
T
NACK
3.1.
SU :S TO
1
STOP
STOP
STOP
1
1
P
1