CS42432-CMZ Cirrus Logic Inc, CS42432-CMZ Datasheet - Page 32

• Manufacturer Part Number: CS42432-CMZ
• Description: IC CODEC 108DB 192KHZ 52-MQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42432-CMZ

• Package / Case: 52-VQFN
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 4 / 6
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 4
• Number Of Dac Outputs: 6
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 4 ADC/6 DAC
• Thd Plus Noise: - 98 dB ADC / - 98 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1608

32
5.5.2
5.6
5.6.1
5.6.2
5.6.3
ADC_SDOUT
AUX_LRCK
AUX_SCLK
AUX_SDIN
DAC_SDIN
SCLK
AUX Port Digital Interface Formats
These serial data lines are used when supporting the TDM Mode of operation with an external ADC or
S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will operate
at 64xFs, where Fs is equal to the ADC sample rate (FS on the TDM interface). If the AUX_SDIN signal is
not being used, it should be tied to AGND via a pull-down resistor.
FS
FS
and must be held valid for at least 1 SCLK period.
Note:
I/O Channel Allocation
Hardware Mode
The AUX port will only operate in the Left-Justified digital interface format and supports bit depths ranging
from 16 to 24 bits (see
AUX_SCLK).
Software Mode
The AUX port will operate in either the Left-Justified or I²S digital interface format with bit depths ranging
from 16 to 24 bits. Settings for the AUX port are made through the register
dress 04h)” on page
I²S
DAC_SDIN
ADC_SDOUT
Digital Input/Output
is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data sample
LSB
MSB
MSB
The ADC does not meet the timing requirements for proper operation in Quad-Speed Mode.
M S B
32 clks
32 clks
AOUT1
AIN1
LSB
LSB
Bit or Word Wide
MSB
MSB
41.
L eft C h a n n el
32 clks
32 clks
AUX1
AOUT2
TDM
TDM
AIN2
Table 4. Serial Audio Interface Channel Allocations
Interface
LSB
LSB
Format
Figure 17 on page 34
Figure 13. TDM Serial Audio Format
MSB
MSB
Figure 14. AUX I²S Format
AOUT3
32 clks
32 clks
AIN3
LSB
LSB
AOUT 1,2,3,4,5,6
AIN 1,2,3,4 (2 additional channels from AUX_SDIN)
L S B
MSB
MSB
32 clks
32 clks
AOUT4
AIN4
LSB
LSB
Analog Output/Input Channel Allocation
256 clks
for timing relationship between AUX_LRCK and
MSB
MSB
M S B
AOUT5
32 clks
32 clks
-
LSB
LSB
from/to Digital I/O
MSB
MSB
R ig ht C h a n n el
AUX2
AOUT6
32 clks
32 clks
-
LSB
LSB
“Miscellaneous Control (Ad-
MSB
MSB
32 clks
32 clks
AUX1
-
LSB
LSB
L S B
MSB
MSB
CS42432
32 clks
32 clks
AUX2
-
DS673F2
LSB
LSB
MSB
MSB
MSB