MAX9851ETM+ Maxim Integrated Products, MAX9851ETM+ Datasheet - Page 34

• Manufacturer Part Number: MAX9851ETM+
• Description: IC CODEC AUDIO STEREO 48TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: Stereo Audior

Specifications of MAX9851ETM+

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 81.5 / 88
• Dynamic Range, Adcs / Dacs (db) Typ: 82 / 87.5
• Voltage - Supply, Analog: 2.6 V ~ 3.3 V
• Voltage - Supply, Digital: 1.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Number Of Adc Inputs: 3
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, I2C)
• Resolution: 18 bit
• Operating Supply Voltage: 1.7 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 6.2 mA
• Thd Plus Noise: - 84 .5 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Stereo Audio CODECs with Microphone, DirectDrive
Headphones, Speaker Amplifiers, or Line Outputs
Set S1SD0 = S1SDI = 0 (register 0x03 and 0x05, bit B6)
before making any mode changes to serial audio inter-
face S1 to ensure proper operation. Similarly, set
S2SD0 = S2SDI = 0 before making any mode changes
to serial audio interface S2. This will disable the serial
interface and ensure that sampling rate and filtering
changes are made properly. Once the desired mode
has been selected through I
enabled. Failure to observe this procedure can
result in the MAX9851/MAX9853 being placed in an
invalid operational mode, leading to unexpected
results.
The MAX9851/MAX9853 power on in low-power shut-
down mode with all signal paths disabled. It is good
practice to configure all I
S2SDI (register 0x03 and 0x05, bit B6) before taking
the MAX9851/MAX9853 out of shutdown. This may
include setting initial volume levels, DAC and ADC
modes of operation, stereo or mono operation, and
audio interface settings. The analog section of the
MAX9851/MAX9853 must be fully operational before
the digital circuitry will function. Enable the charge
pump by setting CPEN = 1 (register 0x1A, bit B4).
Once the MAX9851/MAX9853 have been properly con-
figured, set the global shutdown bit, SHDN, to 1 (regis-
ter 0x1A, bit B7). The MAX9851/MAX9853 are fully
operational 70ms after SHDN is set. Finally, if the DACs
are to be used, program S1SDI and S2SDI as desired
to enable DAC soft-start.
Disable the audio outputs before powering down the
MAX9851/MAX9853 by setting HRMODE and SPMODE
(LOMODE) bits (Register 0x18). Ramping the volume to
maximum attenuation is recommended before disabling
the output amplifiers. Disable the headphone and speak-
er (or line outputs) once the audio is fully attenuated. The
headphone and speaker (or line outputs) can be dis-
abled within 50µs of attenuation without any audible
clicks or pops. Place the MAX9851/MAX9853 in shut-
down after the outputs are disabled.
Set DACLEN and DACREN to 1 (register 0x1B, bit B7
and B6) to enable the left and right DACs while the
S1SDI and S2SDI bits are cleared and the SLD status
bit is low to ensure click/pop suppression, then enable
S1SDI and S2SDI as desired. The stereo DACs can mix
34
Powering On/Off the MAX9851/MAX9853
______________________________________________________________________________________
Changing Serial Audio Interface Modes
2
C registers except S1SDI and
2
C, the interface can be re-
Sigma-Delta DAC
any combination of the four channels of data from the
S1 left/right and S2 left/right signal sources using the
MIXDAL/R bits (register 0x08). Digital signals from the
two interfaces in the 8kHz to 48kHz sample rate range
are combined regardless of S1 and S2 interfaces
modes, even if asynchronous with respect to each
other or MCLK (in DAC-only mode).
When operating in standard stereo audio mode, the
input data stream from each interface is passed through
separate 8x FIR interpolating filters. When operating in
voice mode, the primary interface makes use of an inter-
polating IIR voiceband filter with an optional highpass
component. When operating in mono mode, or when
serial input data is disabled for a digital audio interface,
the unused digital-signal processing filter paths are dis-
abled to minimize supply-current consumption.
The stereo signals at the left and right DAC may be addi-
tionally filtered in any mode with a programmable high-
pass filter to band limit the audio output and block DC.
Set DHPL and DHPR (register 0x07, bits B3–B0) to 01,
10, or 11 to select one of the three highpass filter cutoff
frequencies as shown in Table 2.
Set ADCLEN and ADCREN to 1 (register 0x1B, bit B5 and
B4) to enable the MAX9851/MAX9853’s stereo ADCs. The
ADCs accept analog signals from the line inputs and the
microphone inputs which can be mixed as described in
the Signal Routing section prior to conversion. For ADC
operation, program the enabled digital audio interface(s)
to operate in master mode so that the sampling clock is
generated within the MAX9851/MAX9853.
The maximum signal that will not clip the ADC input is
2V
or line input gain as appropriate. Clipping in the digital
circuitry is indicated by CLD (register 0x00, bit B7).
Table 2. DAC Highpass Filter Modes
P-P
DHPL/DHPR BIT
. If clipping does occur, reduce the microphone
SETTINGS
00
01
10
11
No filtering
55Hz to 91Hz cutoff frequency
171Hz to 279Hz cutoff frequency
327Hz to 533Hz cutoff frequency
FILTER MODE
Sigma-Delta ADC