MAX9867EWV+T Maxim Integrated Products, MAX9867EWV+T Datasheet - Page 38

• Manufacturer Part Number: MAX9867EWV+T
• Description: IC STEREO AUD CODEC LP 30WLP
• Manufacturer: Maxim Integrated Products
• Type: Stereo Audior

Specifications of MAX9867EWV+T

• Data Interface: I²C, Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 1.65 V ~ 1.95 V
• Voltage - Supply, Digital: 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 30-WLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MAX9867EWV+T; MAX9867EWV+TTR

Ultra-Low Power Stereo Audio Codec
Two differential microphone inputs and a low-noise micro-
phone bias for powering the microphones are provided
by the MAX9867. In typical applications, the left micro-
phone records a voice signal and the right microphone
records a background noise signal. In applications that
require only one microphone, use the left microphone
input and disable the right ADC. The microphone signals
are amplified by two stages of gain and then routed to
Table 11. Playback Volume Registers (continued)
Table 12. Microphone Input Registers
38
Left Microphone Gain
Right Microphone Gain
VOLLM/VOLRM
______________________________________________________________________________________
VOLL/VOLR
REGISTER
BITS
Left/Right Playback Mute
VOLLM and VOLRM mute both the DAC and line input audio signals.
0 = Audio playback is unmuted.
1 = Audio playback is muted
Note: VSEN has no effect on the mute function. When VOLLM or VOLRM is set, the output is muted
immediately (ZDEN = 1) or at the next zero-crossing (ZDEN = 0).
Left/Right Playback Volume
VOLL and VOLR control the playback volume for both the DAC and line input audio signals.
Note: Gain settings apply when the headphone amplifier is configured in differential mode. In the single-
ended and capacitorless modes, the actual gain is 5dB lower for each setting.
SETTING
B7
0
0
0x0C
0x0D
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
Microphone Inputs
B6
PAREN
PALEN
GAIN (dB)
+5.5
+4.5
+3.5
+6
+5
+4
+3
+2
+1
-1
-2
-3
-4
0
B5
B4
SETTING
0x1A
0x1B
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
the ADCs. The first stage offers selectable 0dB, 20dB,
or 30dB settings. The second stage is a programmable
gain amplifier (PGA) adjustable from 0dB to 20dB in
1dB steps. Zero-crossing detection is included on the
PGA to minimize zipper noise while making gain
changes. See Figure 5 for a detailed diagram of the
microphone input structure. Table 12 is the microphone
input register.
FUNCTION
B3
GAIN (dB)
PGAMR
PGAML
-10
-12
-14
-16
-18
-20
-22
-26
-30
-34
-38
-5
-6
-8
B2
0x28 to 0x3F
B1
SETTING
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
B0
GAIN (dB)
REGISTER
ADDRESS
MUTE
-54
-62
-42
-46
-50
-58
-66
-70
-74
-78
-82
-84
0x12
0x13