ATF22V10C-15PU Atmel, ATF22V10C-15PU Datasheet - Page 7

IC PLD EE HP 15NS 24-DIP

ATF22V10C-15PU

Manufacturer Part Number
ATF22V10C-15PU
Description
IC PLD EE HP 15NS 24-DIP
Manufacturer
Atmel
Datasheets

Specifications of ATF22V10C-15PU

Programmable Type
EE PLD
Number Of Macrocells
10
Voltage - Input
5V
Speed
15ns
Mounting Type
Through Hole
Package / Case
24-DIP (0.300", 7.62mm)
Logic Family
ATF22V10C
Maximum Operating Frequency
83.3 MHz
Number Of Programmable I/os
10
Delay Time
15 ns
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
Through Hole
Number Of Product Terms Per Macro
16
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Circuit Type
Advanced, Electrically Erasable
Logic Function
Programmable
Logic Type
PLD
Package Type
DIP-24
Special Features
High Speed, Security Fuse
Temperature, Operating, Range
-40 to +85 °C
Voltage, Supply
5 V
Family Name
ATF22V10C
Process Technology
EECMOS
# Macrocells
10
# I/os (max)
10
Frequency (max)
83.3MHz
Propagation Delay Time
15ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATF22V10C-15PU
Manufacturer:
ATM
Quantity:
780
Part Number:
ATF22V10C-15PU
Manufacturer:
ATM
Quantity:
780
Part Number:
ATF22V10C-15PU
Manufacturer:
Atmel
Quantity:
135
Part Number:
ATF22V10C-15PU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
0735U–PLD–7/10
4.7
4.8
5.
6.
7.
Power-up Reset
The registers in the Atmel
V
output buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how V
Figure 4-1.
Preload of Registered Outputs
The ATF22V10C registers are provided with circuitry to allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
Electronic Signature Word
There are 64-bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF22V10C fuse patterns. Once programmed,
fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See “CMOS PLD Programming Hardware
and Software Support” for information on software/programming.
Table 7-1.
Parameter
t
V
CC
1. The V
2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high
3. The clock must remain stable during t
POWER
REGISTERED
OUTPUTS
C LOCK
PR
RST
crossing V
CC
V
rise must be monotonic, and starts below 0.7V
Power-up Reset Timing
Programming/Erasing
R
RST
ST
Description
Power-up Reset Time
Power-up Reset Voltage
, all registers will be reset to the low state. The output state will depend on the polarity of the
CC
actually rises in the system, the following conditions are required:
®
t
ATF22V10Cs are designed to reset during power-up. At a point delayed slightly from
PR
t
W
t
S
PR
Typ
600
3.8
Atmel ATF22V10C(Q)
1,000
Max
4.5
Units
ns
V
7

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