MPC2605ZP66 Freescale Semiconductor, MPC2605ZP66 Datasheet

Page 1

MPC2605/D Rev. 11, 2/2002 Integrated Secondary Cache for Microprocessors That Implement PowerPC Architecture The MPC2605 is a single chip, 256KB integrated look-aside cache with copy-back capability designed for applications using a 60x bus. Using 0.38 m technology along with standard ...

Page 2

MPC2605/D CONTROL 60x BUS CONTROLLER INTERFACE BUS INTERFACE A0 – A31 LRU 2 Integrated Secondary Cache for Microprocessors BLOCK DIAGRAM RD/WR A27, A28 DATA RAM AND RD/ ...

Page 3

A ABB L2 BG DH20 DH19 B CPU3 CFG4 L2 DH23 DH21 BG MISS INH C FDN CPU3 CPU3 V DP2 DD BR DBG CPU2 CPU2 BR DBG DBG ...

Page 4

MPC2605/D PIN DESCRIPTIONS Pin Locations Pin Name 19G, 17H – 19H, 17J – 19J, A0 – A31 17K – 19K, 17L – 19L, 17M – 19M, 17N – 19N, 17P – 19P, 17R – 19R, 18T, 19T, 18U, 19U, 18V, ...

Page 5

PIN DESCRIPTIONS (continued) Pin Locations Pin Name 2D CPU2 BR 2C CPU3 BR 1U CPU4 BR 1F CPU DBG 3D CPU2 DBG 3C CPU3 DBG 2T CPU4 DBG 11A – 13A, 15A – 18A, DL0 – DL31 11B – 17B, ...

Page 6

MPC2605/D PIN DESCRIPTIONS (continued) Pin Locations Pin Name 3B L2 MISS INH 2N L2 TAG CLR 3N L2 UPDATE INH 3J PWRDN 1N SRESET 1E 3K TBST TRST 3L 17F – 19F * TSIZ0 ...

Page 7

ABSOLUTE MAXIMUM RATINGS Rating Power Supply Voltage Voltage Relative Output Current (per I/O) Power Dissipation (Note 2) Temperature Under Bias Junction Temperature Storage Temperature NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. ...

Page 8

MPC2605/D CAPACITANCE (f = 1.0 MHz Parameter Input Capacitance Output Capacitance Input/Output Capacitance PACKAGE THERMAL CHARACTERISTICS Thermal Resistance Junction to Ambient (Still Air, Test Board with Two Internal Planes) Thermal Resistance Junction to Ambient (200 lfpm, Test Board ...

Page 9

MPC2605 RESPONSE TO 60x TRANSFER ATTRIBUTES TT0 – TT4 TBST CI WT X1X10 X1X10 X1010 X1010 00110 00110 00X10 ...

Page 10

MPC2605/D MPC2605 RESPONSE TO CHIPSET TRANSFER ATTRIBUTES TT0 – TT4 Tag Status 00100 Hit Clean Invalidate line X0010 X1110 00100 Hit Dirty ARTRY and L2 BR write back data, invalidate line (see Note) X0010 X1110 00000 Hit Clean No action ...

Page 11

SYSTEM USAGE AND REQUIREMENTS The MPC2605 is a high-performance look-aside cache. A look-aside cache is defined as a cache that resides on the same bus as the processor, memory controller, DMA bridge, and arbiter. The advantage of a look-aside cache ...

Page 12

MPC2605/D systems such as these, transactions generated by the DMA bridge are true memory requests that have data tenures associated with them. These are called snoop data tenures. Because these two types of systems are fundamentally different, the MPC2605 must ...

Page 13

AACK is asserted. This cycle is referred to as the ARTRY window, since it is the cycle that all devices sample ARTRY to determine if the address tenure has been successfully completed address tenure is ...

Page 14

MPC2605/D 2-1-1-1 response. However, even though the MPC2605 has this ability dependent on the system to allow this quick of a response to occur. As discussed above, a data tenure cannot start until the master has been given ...

Page 15

If transaction one is a cache hit, the MPC2605 will be the slave device for the transaction. Since, for burst operations, the MPC2605 always asserts TA for four consecutive clock cycles, the end of the data tenure for transaction one ...

Page 16

MPC2605/D the L2 BR signal is sampled first already asserted, then it is clear that another device is also in a castout situation. The late device will wait until negated before continuing in ...

Page 17

HRESET asserted at reset, the MPC2605 will invalidate all cache entries when PWRDN is negated negated at reset, the MPC2605 will leave all cache entries as they were prior to the assertion ...

Page 18

MPC2605/D READ HIT/WRITE HIT Figure 1 shows a read hit from an idle bus state. The MPC2605 asserts L2 CLAIM the cycle after TS to inform the memory controller that there is a cache hit and the cache will control ...

Page 19

MULTIPLE READ/WRITE HITS (NORMAL BUS MODE) Figure illustration of MPC2605 pipeline depth limit with multiple read hits. The MPC2605 supports only one level of address pipelining for data CLK CPU – A31 TBST L2 ...

Page 20

MPC2605/D READ MISS (NORMAL BUS MODE) Figure illustration of the MPC2605 pipeline depth with a read miss followed by a read hit. For illustration purposes, the read miss is shown as a 3-1-1-1 response from memory. AACK ...

Page 21

MULTIPLE READ HITS (FAST L2 MODE) Back-to-back pipelined burst read hits for the MPC2605 in Fast L2 mode, also called data streaming mode, are shown in Figure 4. Note that CPU DBG is negated, except for the cycles coincident with ...

Page 22

MPC2605/D WRITE THROUGH BURST WRITE HIT Figure 5 shows the fastest possible burst write hit to a write-through mode L2 cache line, read miss or write miss processing that replaces a clean line. For these operations, the MPC2605 will not ...

Page 23

READ/WRITE MISS Figure illustration of a processor read or write miss that causes the MPC2605 to replace a dirty line asserted two clocks after TS. The dirty data to be replaced is moved into ...

Page 24

MPC2605/D READ/WRITE SNOOP HIT (DIRTY L2 LINE) Figure illustration of a read or write snoop to a cache line that is dirty in the L2, but is not dirty in the processor’s cache. When a snoop hits ...

Page 25

READ/WRITE SNOOP HIT (DIRTY L2 AND PROCESSOR LINE) An illustration of a read or write snoop hit to a dirty L2 cache line is shown in Figure 8. The processor has a dirty copy of the cache line. In this ...

Page 26

MPC2605/D READ HIT/WRITE HIT (WITHOUT CPU DBG PARKED) Most of the previous examples have assumed CPU DBG is asserted in the same cycle that the processor asserts TS. This implies CPU DBG is parked. In some CLK CPU BG TS ...

Page 27

AC OPERATING CONDITIONS AND CHARACTERISTICS FOR THE TEST ACCESS PORT (IEEE 1149.1) (T Input Timing Measurement Reference Level 1.5 V Input Pulse Levels . . . . . . . . . . ...

Page 28

MPC2605/D INSTRUCTION SET A five-pin IEEE Standard 1149.1 Test Port (JTAG) is included on this device. When the TAP (Test Access Port) controller is in the SHIFT-IR state, the instruction register is placed between TDI and TDO. In this state, ...

Page 29

BYPASS TAP INSTRUCTION The BYPASS instruction is the default instruction loaded at power up. This instruction will place a single shift register between TDI and TDO during the SHIFT-DR state of the TAP controller. This allows the board level scan ...

Page 30

MPC2605/D BIT NUMBER The order of the boundary scan chain. Bit 0 is the closest to TDO. BIT/PIN NAME The name of the physical pin. For an output enable cell, this is the name of the corresponding output enable. BIT/PIN ...

Page 31

Bit Bit/Pin Bit/Pin No. Name Type 46 FDN I DBG Input I I CLAIM Output 51 CPU DBG Input 52 AACK I I/O 54 ARTRY I I/O ...

Page 32

MPC2605/D Bit Bit/Pin Bit/Pin No. Name Type 118 A4 I/O 119 A5 I/O 120 A6 I/O 121 A7 I/O 122 A8 I/O 123 A9 I/O 124 A10 I/O 125 A11 I/O 126 A12 I/O 127 A31 I/O 128 A30 I/O ...

Page 33

... Motorola Prefix Part Number Full Part Numbers — MPC2605ZP66 MOTOROLA Integrated Secondary Cache for Microprocessors ORDERING INFORMATION (Order by Full Part Number) MPC 2605 Blank = Trays Tape and Reel Speed ( MHz MHz) Package (ZP = PBGA) MPC2605ZP83 MPC2605ZP66R MPC2605ZP83R That Implement PowerPC Architecture MPC2605/D ...

Page 34

MPC2605 TOP VIEW ...

Page 35

THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA Integrated Secondary Cache for Microprocessors That Implement PowerPC Architecture MPC2605/D 35 ...

Page 36

HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon ...