Z8018010FSC Zilog, Z8018010FSC Datasheet - Page 44

IC 10MHZ Z180 CMOS ENH MPU 80QFP

Z8018010FSC

Manufacturer Part Number
Z8018010FSC
Description
IC 10MHZ Z180 CMOS ENH MPU 80QFP
Manufacturer
Zilog
Datasheet

Specifications of Z8018010FSC

Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3014

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ASCI Block Diagram
ASCI Registers
PS014004-1106
TXA
RXA
RTS
CTS
DCD
ASCI Transmit Shift Register 0 (TSR0, TSR1)—When the ASCI Transmit Shift
Register (
shifted out to the
automatically loaded from
available for transmission,
register is not program accessible.
ASCI Transmit Data Register 0,1 (TDR0, TDR1)— I/O
address =
transferred to the
the previous byte of data. The ASCI transmitter is double buffered.
0
0
0
0
0
ASCI Transmit Data Register
Ch 0: TDR0
ASCI Transmit Shift Register*
Ch 0: TSR0
ASCI Receive Data FIFO
Ch 0: RDR0
ASCI Receive Shift Register*
Ch 0: RSR0 (8)
ASCI Control Register A
Ch 0: CNTLA0 (8)
ASCI Control Register B
Ch 0: CNTB0 (8)
ASCI Status FIFO
Ch 0
ASCI Status Register
Ch 0: STAT0 (8)
TSR
06h, 07h
) receives data from the ASCI Transmit Data Register (
TxA
TSR
. Data written to the ASCI Transmit Data Register is
CKA
CKA
Figure 27. ASCI Block Diagram
pin. When transmission is completed, the next byte (if available) is
as soon as
0
1
TDR
TSR IDLE
Internal Address/Data Bus
Interrupt Request
into
TSR
Baud Rate
Generator 0
Baud Rate
Generator 1
ASCI
Control
TSR
s by outputting a continuous High level. This
is empty. Data can be written while
and the next transmission starts. If no data is
φ
ASCI Transmit Data Register
Ch 1: TDR1
ASCI Transmit Shift Register*
Ch 1: TSR1
ASCI Receive Data FIFO
Ch 1: RDR1
ASCI Receive Shift Register*
Ch 1: RSR1 (8)
ASCI Control Register A
Ch 1: CNTLA1 (8)
ASCI Control Register B
Ch 1: CNTB1 (8)
ASCI Status FIFO
Ch 1
ASCI Status Register
Ch 1: STAT1 (8)
Note: *Not Program
Accessible.
Microprocessor Unit
TDR
TXA
RXA
CTS
TSR
), the data is
1
1
1
is shifting out
Architecture
Z80180
38

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