MPC8572ECVTAULD Freescale Semiconductor, MPC8572ECVTAULD Datasheet - Page 3

• Manufacturer Part Number: MPC8572ECVTAULD
• Description: MPU POWERQUICC III 1023-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8572ECVTAULD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
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Two 64-bit DDR2/DDR3 memory controllers
— Programmable timing supporting DDR2 and DDR3 SDRAM
— 64-bit data interface per controller
— Four banks of memory supported, each up to 4 Gbytes, for a maximum of 16 Gbytes per
— DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports
— Full ECC support
— Page mode support
— Contiguous or discontiguous memory mapping
— Cache line, page, bank, and super-bank interleaving between memory controllers
— Read-modify-write support for RapidIO atomic increment, decrement, set, and clear
— Sleep mode support for self-refresh SDRAM
— On-die termination support when using DDR2 or DDR3
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access through JTAG port
— 1.8-V SSTL_1.8 compatible I/O
— Support 1.5-V operation for DDR3. The detail is TBD pending on official release of
— Support for battery-backed main memory
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture.
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts per processor with 32-bit messages
— Supports connection of an external interrupt controller such as the 8259 programmable
— Four global high resolution timers/counters per processor that can generate interrupts
— Supports a variety of other internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing.
– Four inbound windows plus a default window on Serial RapidIO®
– Four outbound windows plus default translation for PCI Express
– Eight outbound windows plus default translation for Serial RapidIO with segmentation and
controller
– Up to 32 simultaneous open pages for DDR2 or DDR3
transactions
appropriate industry specifications.
interrupt controller
sub-segmentation support
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Overview
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