MPC8555ECPXAJD Freescale Semiconductor, MPC8555ECPXAJD Datasheet - Page 27

• Manufacturer Part Number: MPC8555ECPXAJD
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8555ECPXAJD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8555CDS - BOARD EVALUATION CDS FOR 8555CWH-PPC-8555N-VX - BOARD EVAL QUICCSTART MPC8555CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540CWH-PPC-8555N-VE - EVALUATION SYSTEM QUICC MPC8555E
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

8.2.3.2
Table 23
Figure 11
Freescale Semiconductor
At recommended operating conditions with LV
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise and fall time
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
for inputs and t
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
(K) going to the high (H) state or setup time. Also, t
input signals (D) went invalid (X) relative to the t
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t
used with the appropriate letter: R (rise) or F (fall).
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
provides the MII receive AC timing specifications.
shows the MII receive AC timing diagram.
MII Receive AC Timing Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter/Condition
RXD[3:0]
RX_CLK
RX_DV
RX_ER
MRX
Table 23. MII Receive AC Timing Specifications
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
Figure 11. MII Receive AC Timing Diagram
t
t
MRXH
MRDVKH
DD
of 3.3 V ± 5%.
t
MRX
MRX
MRDXKL
clock reference (K) going to the low (L) state or hold time. Note that, in
Valid Data
t
MRXR
symbolizes MII receive timing (GR) with respect to the time data
t
MRXH
Symbol
t
t
MRDVKH
MRDXKH
t
t
MRXF
t
MRX
, t
MRX
MRXF
/t
MRX
2
for outputs. For example, t
1
(first two letters of functional block)(signal)(state) (reference)(state)
2,3
t
MRDXKH
t
MRXR
10.0
10.0
Min
1.0
35
—
—
Ethernet: Three-Speed, MII Management
Typ
400
40
—
—
—
—
MRDVKH
MRX
symbolizes MII
Max
4.0
—
—
65
—
—
clock reference
Unit
ns
ns
ns
ns
ns
%
27