MPC603RRX266TC Freescale Semiconductor, MPC603RRX266TC Datasheet - Page 2

• Manufacturer Part Number: MPC603RRX266TC
• Description: IC MPU 32BIT 266MHZ 255-CBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC603RRX266TC

• Processor Type: MPC603e PowerPC 32-Bit
• Speed: 266MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

The known errata as of the date of this document are summarized below.
Electrical and Thermal Characteristics
This section provides any changes to the AC and DC electrical speciÞcations and thermal characteristics for the PID6-603e parts
described herein.
DC Electrical Characteristics
This section describes the changed thermal operating conditions for the PID7t-603e part numbers described herein.
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Snoop copyback causes dcbi to
broadcast wrong address.
Competition for reservation
with lwarx/stwcx may cause
live-lock
Touch load causes incorrect
address to appear on memory
bus
Write-thru stores followed by
dcbz followed by a snoop, all
to the same cache line, may
cause incoherency.
The broadcasting of dcbz
instructions may retry snoop
accesses indeÞnately.
Junction temperature
Problem
Note: 1. Parts with TC sufÞx only.
Characteristic
PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor, Inc.
A snoop which causes a copy-
back and occurs in a one cycle
window near a dcbi causes the
dcbi to broadcast the address
of the snoop copyback.
The problem occurs when two
processors are competing on
the bus for a reservation, and
the bus is operating with
address pipelining
A touch load (dcbt) preceded
by an instruction that generates
an exception causes a random
address to appear on the mem-
ory bus
The sequence of write-thru
stores followed by dcbz fol-
lowed by a snoop, all to the
same cache line, may cause
incoherency.
A sequence of broadcast bcbz
instructions may retry snoop
accesses indeÞnately.
. Recommended Operating Conditions
Description
Symbol
T
J
Only systems using both soft-
ware and hardware coherency
simultaneously.
System Hang
Systems issuing instructions
which generate mmu excep-
tions one cycle before using a
touch load instruction
The write-thru store is com-
pleted after the dcbz.
Snoop originator may timeout.
-40 to 105
Value
Impact
PID7v-603e Specification Variances
Unit
° C
Use software semaphores
rather than rely on dcbi to
invalidate cache lines shared
across multiple processors.
Insert a bus clockÕs worth of
no-ops before lwarx
Disable touch loads with
NOOPTI bit in HID0.
Store zeroes rather than rely on
dcbz to zero cache lines in
areas of memory that are
marked as write-thru and can
be accessed via multiple logi-
cal addresses.
Disable broadcasting of dcbz
by marking the memory space
being addressed by the dcbz
instruction as not global in the
BAT or PTE.
Notes
Solutions