MPC8347CVRADDB Freescale Semiconductor, MPC8347CVRADDB Datasheet - Page 37

• Manufacturer Part Number: MPC8347CVRADDB
• Description: IC MPU PWRQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8347CVRADDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 19
Freescale Semiconductor
Local bus clock to output valid
Local bus clock to output high impedance for LAD/LDP
Notes:
1. The symbols for timing specifications follow the pattern of t
2. All timings are in reference to the falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or the rising edge
3. All signals are measured from OV
4. Input timings are measured at the pin.
5. t
6. t
7. t
8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered
9. DLL bypass mode is not recommended for use at frequencies above 66 MHz.
and t
for the input (I) to go invalid (X) with respect to the time the t
(1). Also, t
(O) going invalid (X) or output hold time.
of LCLK0 (for all other inputs).
signaling levels.
the load on the LAD output pins.
load on the LAD output pins.the
output pins.
through the component pin is less than or equal to the leakage current specification.
LBOTOT1
LBOTOT2
LBOTOT3
(first two letters of functional block)(reference)(state)(signal)(state)
provides the AC test load for the local bus.
should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than
should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the
should be used when RCWH[LALE] is set and when the load on the LALE output pin equals to the load on the LAD
LBKHOX
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Table 35. Local Bus General Timing Parameters—DLL Bypass
symbolizes local bus timing (LB) for the t
Parameter
Output
DD
/2 of the rising/falling edge of LCLK0 to 0.4 × OV
Figure 19. Local Bus C Test Load
Z
0
= 50 Ω
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
LBK
LBK
clock reference (K) to go high (H), with respect to the output
clock reference (K) goes high (H), in this case for clock one
Symbol
t
t
LBKHOZ
LBKLOV
1
R
L
= 50 Ω
Min
—
—
LBIXKH1
DD
OV
of the signal in question for 3.3 V
9
DD
symbolizes local bus timing (LB)
(continued)
/2
Max
3
4
Unit
ns
ns
for inputs
Local Bus
Notes
3
8
37