MPC880ZP133 Freescale Semiconductor, MPC880ZP133 Datasheet - Page 2

• Manufacturer Part Number: MPC880ZP133
• Description: IC MPU POWERQUICC 133MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC880ZP133

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 133MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Overview
1
The MPC885/MPC880 is a versatile single-chip integrated microprocessor and peripheral combination
that can be used in a variety of controller applications and communications and networking systems. The
MPC885/MPC880 provides enhanced ATM functionality, an additional fast Ethernet controller, a USB,
and an encryption block.
Table 1
2
The MPC885/MPC880 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx
core, a system integration unit (SIU), and a communications processor module (CPM).
The following list summarizes the key MPC885/MPC880 features:
2
MPC885
MPC880
•
•
•
Part
Overview
Features
Embedded MPC8xx core up to 133 MHz
Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)
— The 133-MHz core frequency supports 2:1 mode only.
— The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes.
Single-issue, 32-bit core (compatible with the Power Architecture definition) with thirty-two
32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch and without conditional
— 8-Kbyte data cache and 8-Kbyte instruction cache (see
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
— Advanced on-chip emulation debug mode
shows the functionality supported by MPC885/MPC880.
execution.
– Instruction cache is two-way, set-associative with 256 sets in 2 blocks
– Data cache is two-way, set-associative with 256 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
– Caches are physically addressed, implement a least recently used (LRU) replacement
spaces and 16 protection groups
I Cache
cache blocks.
algorithm, and are lockable on a cache block basis.
Cache (Kbytes)
8
8
D Cache
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
8
8
10BaseT
Up to 3
Up to 2
Ethernet
Table 1. MPC885 Family
10/100
2
2
SCC
3
2
SMC
2
2
Table
USB
1
1
1)
UTOPIA interface
UTOPIA interface
Serial ATM and
Serial ATM and
ATM Support
Freescale Semiconductor
Security
Engine
Yes
No