IDT79RC32T355-150DH IDT, Integrated Device Technology Inc, IDT79RC32T355-150DH Datasheet - Page 10

• Manufacturer Part Number: IDT79RC32T355-150DH
• Description: IC MPU 32BIT CORE 150MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32T355-150DH

• Processor Type: RISC 32-Bit
• Speed: 150MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32T355-150DH

JTAG_TMS
EJTAG_PCST[0]
EJTAG_PCST[1]
EJTAG_PCST[2]
EJTAG_DCLK
EJTAG_TRST_N
JTAG_TRST_N
Debug
INSTP
CPUP
DMAP[0]
DMAP[1]
IDT 79RC32355
Name
Type I/O Type
O
O
O
O
O
O
O
O
I
I
I
Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected
Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected
Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected
Low Drive PC trace clock. This is used to capture address and data during EJTAG/ICE mode. EJTAG/ICE enable is selected during
Low Drive Instruction or Data Indicator. This signal is driven high during CPU instruction fetches and low during CPU data transac-
Low Drive CPU or DMA Transaction Indicator. This signal is driven high during CPU transactions and low during DMA transactions
Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the
Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the
STI
STI
STI
JTAG Mode Select. This input signal is decoded by the tap controller to control test operation. This signal requires an
external resistor, listed in Table 16.
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal
requires an external resistor, listed in Table 16.
Primary function: General Purpose I/O, GPIOP[10].
1st Alternate function: UART channel 1 data terminal ready, U1DTRN.
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal
requires an external resistor, listed in Table 16.
Primary function: General Purpose I/O, GPIOP[11]. At reset, this pin defaults to primary function GPIOP[11].
1st Alternate function: UART channel 1 data set ready, U1DSRN.
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal
requires an external resistor, listed in Table 16.
Primary function: General Purpose I/O, GPIOP[12].
1st Alternate function: UART channel 1 request to send, U1RTSN.
reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal requires
an external resistor, listed in Table 16.
Primary function: General Purpose I/O, GPIOP[13].
1st Alternate function: UART channel 1 clear to send, U1CTSN.
EJTAG Test Reset. EJTAG_TRST_N is an active-low signal for asynchronous reset of only the EJTAG/ICE controller.
EJTAG_TRST_N requires an external pull-up on the board. EJTAG/ICE enable is selected during reset using the boot con-
figuration and overrides the selection of the Primary and Alternate functions. This signal requires an external resistor, listed
in Table 16.
Primary: General Purpose I/O, GPIOP[31]
1st Alternate function: DMA finished output, DMAFIN.
JTAG Test Reset. JTAG_TRST_N is an active-low signal for asynchronous reset of only the JTAG boundary scan control-
ler. JTAG_TRST_N requires an external pull-down on the board that will hold the JTAG boundary scan controller in reset
when not in use if selected. JTAG reset enable is selected during reset using the boot configuration and overrides the
selection of the Primary and Alternate functions.
Primary function: General Purpose I/O, GPIOP[2].
1st Alternate function: UART channel 0 ring indicator, U0RIN.
tions on the memory and peripheral bus.
on the memory and peripheral bus if CPU/DMA Transaction Indicator Enable is enabled. CPU/DMA Status mode enable is
selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions.
Primary function: General Purpose I/O, GPIOP[4].
1st Alternate function: UART channel 0 data terminal ready U0DTRN.
selection of the Primary and Alternate functions.
Primary function: General Purpose I/O, GPIOP[23].
1st Alternate function: TXADDR[1].
selection of the Primary and Alternate functions.
Primary function: General Purpose I/O, GPIOP[25].
1st Alternate function: RXADDR[1].
Table 1 Pin Descriptions (Part 6 of 8)
10 of 47
Description
May 25, 2004