IDT79RC32V334-133BBG IDT, Integrated Device Technology Inc, IDT79RC32V334-133BBG Datasheet - Page 11

• Manufacturer Part Number: IDT79RC32V334-133BBG
• Description: IC PROC 32BIT CORE 133MHZ 256BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32V334-133BBG

• Processor Type: RISC 32-Bit
• Speed: 133MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 79RC32V334-133BBG

Mode Bit Settings to Configure Controller on Reset
Debug Signals
debug_cpu_dma_n
debug_cpu_ack_n
debug_cpu_ads_n
debug_cpu_i_d_n
IDT 79RC32334—Rev. Y
The following table lists the mode bit settings to configure the controller on cold reset.
Name
ejtag_pcst[2:0]
debug_cpu_i_d_n
debug_cpu_ack_n
debug_cpu_ads_n
debug_cpu_dma_n
mem_addr[17]
Type
I/O
I/O
I/O
I/O
Pin
Status
Reset
State
Z
Z
Z
Z
Mode Bit
2:0 MSB (2)
Capability
Strength
Drive
Low
Low
Low
Low
3
4
5
6
7
Table 2 Boot-Mode Configuration Settings (Part 1 of 2)
Debug CPU versus DMA Negated
De-assertion high during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transac-
tion was generated from the CPU.
Assertion low during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction
was generated from DMA.
Alternate function: modebit[6].
Debug CPU Acknowledge Negated
Indicates either a data acknowledge to the CPU or DMA.
Alternate function: modebit[4].
Debug CPU Address/Data Strobe Negated
Assertion indicates that either a CPU or a DMA transaction is beginning and that the mem_data[31:4] bus
has the current block address.
Alternate function: modebit[5].
Debug CPU Instruction versus Data Negated
Assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a
CPU or DMA data transaction.
De-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a
CPU instruction transaction.
Alternate function: modebit[3].
Clock Multiplier
MasterClock is multiplied internally to gener-
ate PClock
EndBit
Reserved
Reserved
TmrIntEn
Enables/Disables the timer interrupt on Int*[5]
Reserved for future use
Table 1 Pin Description (Part 7 of 7)
Description
11 of 30
Description
Value
0
1
2
3
4
5
6
7
0
1
0
0
0
1
1
Multiply by 2
Multiply by 3
Multiply by 4
Reserved
Reserved
Reserved
Reserved
Reserved
Little-endian ordering
Big-endian ordering
Enables timer interrupt
Disables timer interrupt
Mode Setting
August 31, 2004