IDT79R3041-20J IDT, Integrated Device Technology Inc, IDT79R3041-20J Datasheet - Page 3

• Manufacturer Part Number: IDT79R3041-20J
• Description: IC MPU 32BIT 5V 20MHZ 84-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79R3041-20J

• Processor Type: RISC 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79R3041-20J

System Control Co-Processor
processor, CP0. CP0 manages the exception handling capa-
bility of the R3041, the virtual to physical address mapping of
the R3041, and the programmable bus interface capabilities
of the R3041. These topics are discussed in subsequent
sections.
members of the RISController family, but instead performs the
same virtual to physical address mapping of the base version
of the RISController family.
distinct kernel and user mode operation, but do not require
page management software or an on-chip TLB, leading to a
simpler software model and a lower-cost processor.
in Figure 3. Note that the reserved address spaces shown are
for compatibility with future family members; in the current
family members, references to these addresses are trans-
lated in the same fashion as their respective segments, with
no traps or exceptions taken.
system designer can implement a distinction between the
user tasks and the kernel tasks, without having to execute
page management software. This distinction can take the
form of physical memory protection, accomplished by ad-
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
The R3041 also integrates on-chip a System Control Co-
The R3041 does not include the optional TLB found in other
The memory mapping used by these devices is illustrated
When using the base versions of the architecture, the
0xffffffff
0xfff00000
0xffefffff
0xc0000000
0xbfffffff
0xa0000000
0x9fffffff
0x80000000
0x7fffffff
0x7ff00000
0x7fefffff
0x00000000
Kernel Uncached
Kernel Reserved
These devices still support
User Reserved
Kernel Cached
Kernel Cached
Figure 3. Virtual to Physical Mapping of Base Architecture Versions
Kernel/User
VIRTUAL
Cached
(kseg2)
(kseg1)
(kseg0)
(kuseg)
1MB
1MB
dress decoding, or in other system specific forms. In systems
which do not wish to implement memory protection, and wish
to have the kernel and user tasks operate out of a single
unified memory space, upper address lines can be ignored by
the address decoder, and thus all references will be seen in
the lower gigabyte of the physical address space.
These resources are detailed in the R3041 User's Manual.
They allow kernel software to directly control activity of the
processor internal resources and bus interface, and include:
• Cache Configuration Register: This register controls the
• Bus Control Register: This register controls the behavior
• Count and Compare Registers: Together, these two
• Port Size Control Register: This register allows the kernel
data cache block size and miss refill algorithm.
of the various bus interface signals.
registers implement a programmable 24-bit timer, which
can be used for DRAM refresh or as a general purpose
timer.
to indicate the port width of reads and writes to various sub-
regions of the physical address space. Thus, the R3041 can
interface directly with 8-, 16-, and 32-bit memory ports,
including a mix of sizes, for both instruction and data
references, without requiring additional external logic.
The R3041 adds additional resources into the on-chip CP0.
Kernel Reserved
User Reserved
Kernel Cached
Inaccessible
PHYSICAL
Kernel/User
Kernel Boot
1023 MB
2047 MB
Cached
512 MB
512 MB
and I/O
Tasks
Tasks
1MB
1MB
COMMERCIAL TEMPERATURE RANGE
0xffffffff
0xfff00000
0xffefffff
0xc0000000
0xbfffffff
0xbff00000
0xbfefffff
0x40000000
0x3fffffff
0x20000000
0x1fffffff
0x00000000
2905 drw 03
3