EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 91

• Manufacturer Part Number: EZ80190AZ050EG
• Description: IC WEBSERVER 50MHZ XTEMP 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3865; EZ80190AZ050EG

PS006614-1208
UART Modem Status Registers
Table 36. UART Line Status Registers
Bit
Position
1
OE
0
DR
Bit
Reset
CPU Access
Note: R = Read Only.
The UART Modem Status Registers, listed in
UART signals.
Value
0
1
0
1
Description
The received character at the top of the FIFO does not contain
an overrun error. This bit is reset to 0 when the UARTx_LSR
register is read.
An overrun error is detected. If the FIFO is not enabled, this
error indicates the data in the receive buffer register was not
read before the next character was transferred into the receiver
buffer register. If the FIFO is enabled, this error indicates the
FIFO was already full when an additional character was
received by the receiver shift register. The character in the
receiver shift register is not placed into the receive FIFO.
This bit is reset to 0 when the UARTx_RBR register is read or
when all bytes are read from the receive FIFO.
Data Ready
If the FIFO is not enabled, this bit is set to 1 when a complete
incoming character is transferred into the receiver buffer
register from the receiver shift register. If the FIFO is enabled,
this bit is set to 1 when a character is received and transferred
to the receive FIFO.
X
R
7
X
R
6
X
R
5
(UART0_MSR = C6h, UART1_MSR = D6h)
R
X
4
Table
Universal Asynchronous Receiver/Transmitter
36, are used to show the status of the
R
X
3
R
X
2
Product Specification
R
X
1
X
R
0
eZ80190
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