Z8018006VEG Zilog, Z8018006VEG Datasheet - Page 32

• Manufacturer Part Number: Z8018006VEG
• Description: IC 6MHZ Z180 CMOS ENH MPU 68PLCC
• Manufacturer: Zilog

Specifications of Z8018006VEG

• Processor Type: Z180
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 6 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Table 8. Z80180-8 AC Characteristics (continued)
PS014004-1106
No
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
P
P
t
t
t
t
t
Symbol Item
INTS
NMIW
BRS
BRH
BAD1
BAD2
BZD
MEWH
MEWL
RFD1
RFD2
HAD1
HAD2
DRQS
DRQH
TED1
TED2
ED1
ED2
Er
Ef
TOD
STDI
STDE
WEH
WEL
INT Hold Time from Ø Fall
NMI Pulse Width
BUSREQ Set-up Time to Ø Fall
BUSREQ Hold Time from Ø Fall
Ø Rise to BUSACK Fall Delay
Ø Fall to BUSACK Rise Delay
Ø Rise to Bus Floating Delay Time
MREQ Pulse Width (High)
MREQ Pulse Width (Low)
Ø Rise to RFSH Fall Delay
Ø Rise to RFSH Rise Delay
Ø Rise to HALT Fall Delay
Ø Rise to HALT Rise Delay
/DREQi Set-up Time to Ø Rise
/DREQi Hold Time from Ø Rise
Ø Fall to TENDi Fall Delay
Ø Fall to TENDi Rise Delay
Ø Rise to E Rise Delay
Ø Fall or Rise to E Fall Delay
E Pulse Width (High)
E Pulse Width (Low)
Enable Rise Time
Enable Fall Time
Ø Fall to Timer Output Delay
CSIO Transmit Data Delay Time (Internal Clock
Operation)
CSIO Transmit Data Delay Time (External Clock
Operation)
Z80180-8
Min
40
100
40
40
–
–
–
90
100
–
–
–
–
40
40
–
–
–
–
65
130
–
–
–
–
–
–
–
–
–
–
80
–
60
70
200
200
7.5tcy
c
+200
Max
70
70
90
80
80
80
–
60
70
–
–
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Microprocessor Unit
Architecture
Z80180
26