GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 18

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

Intel
Errata
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18
®
IXP1200 Network Processor
PCI CBE# Values on I/O Reads
When the StrongARM* core accesses the PCI bus through an I/O read with transactions that are
not in longword lengths, the CBE# field will have incorrect values.
On data sizes less than a longword, incorrect data will be transferred.
Limit data sizes to longwords.
Fixed
Deleted. Included in Errata 12.
PCI Extended Capabilities Support Detection
Bit 20 of the PCI_CMD_STAT, which is aliased as PCI Status Register bit 4, is improperly
hardwired to 0, causing improper detection of IXP1200 PCI Extended Capabilities. This is a PCI
2.2 compatibility issue for customers who may be using the IXP1200 in a PC architecture using
PCI BIOS and/or PCI plug-and-play drivers.
PCI Extended Capabilities support in the IXP1200 may not be properly detected by BIOS and/or
PCI plug-and-play drivers. The IXP1200 may fail Microsoft’s Hardware Compatibility Tests.
None. Even though Extended Capabilities are supported, there is no method via register reads to
determine that they are supported. You may, however, use these features without confirmation.
Fixed
Flow-Thru SRAM Read-Modify-Write
When the IXP1200 is configured with Flow-Thru SRAMs, a StrongARM* core byte write
operation to SRAM will write incorrect data to the location that the operation was performed on.
Incorrect data will be in the SRAM location that the StrongARM* core operation byte write was
performed on.
When using Flow-Thru SRAMs, do not do a byte write operation form the StrongARM* core or
use pipelined SRAMs.
Fixed
Hold Time Issues for all PCI Signals (Both Bused and Control)
The PCI Local Bus Specification, Revision 2.2, specifies a minimum Hold Time of 0 ns in Section
7.6.4.2. The IXP1200 requires a minimum hold time of 1.0 ns (t
Clk).
System designers must constrain their design to tighter than worst-case PCI timing. One recom-
mendation is to limit the trace length of the PCI bus resulting in a reduction of Tprop.
None.
NoFix
h
- Input Signal Hold Time from
Specification Update