MPC855TVR50D4 Freescale Semiconductor, MPC855TVR50D4 Datasheet - Page 3

• Manufacturer Part Number: MPC855TVR50D4
• Description: IC MPU POWERQUICC 50MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC Ir

Specifications of MPC855TVR50D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 8KB
• Cpu Speed: 50MHz
• Embedded Interface Type: Ethernet, I2C, SPI, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 357
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MOTOROLA
•
— Receive VP/VC connection lookup mechanisms, including:
— Independent transmit/receive buffer descriptor ring data structures for each connection
— Interrupt report per channel using exception queue
— Supports 53-byte or up to 64-byte (expanded) ATM cells
— AAL5 segmentation and reassembly (SAR) features for segmentation
— AAL5 segmentation and reassembly (SAR) features for reassembly:
— AAL0 features for transmit include the following:
— AAL0 features for receive include the following:
Embedded MPC8xx core with 106 MIPS at 80 MHz (using Dhrystone 2.1)
— Single-issue, 32-bit version of the embedded MPC8xx core (fully compatible with the
– Transmission convergence (TC) function for T1/E1/ADSL lines
– Cell delineation
– Cell payload scrambling/descrambling
– Automatic idle/unassigned cell insertion/stripping
– Header error control (HEC) generation, checking, and statistics
– Glueless interface to Motorola CopperGold ADSL transceiver
– Internal sequential lookup table supporting up to 32 connections
– Support for up to 64K connections using external memory via address compression or
– Segment CPCS_PDU directly from system memory
– CPCS_PDU padding
– CRC32 generation
– Automatic last cell marking (in PTI field of cell header)
– Automatic CS_UU, CPI, and LENGTH insertion in last cell
– Reassembles CPCS_PDU directly into system memory
– Removes CPCS_PDU padding
– CRC32 checking
– CS_UU, CPI, and LENGTH reporting
– CLP and congestion reporting
– Interrupts per buffer or per message
– Error reporting, including CRC, length mismatch, message abort
– Transmits user-defined cell from transmit emory buffer
– Automatic HEC generation
– Optional CRC10 insertion
– Copies entire cell into receive memory buffer
– Provides interrupt per cell
– Optional CRC10 checking
PowerPC user instruction set architecture; refer to the Programming Environments Manual for
32-Bit Implementations of the PowerPC Architecture for more information) with 32- x 32-bit
content-addressable memory (CAM)
MPC855T Communications Controller Technical Summary
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MPC855T Key Features
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