CY8C20646A-24LTXI Cypress Semiconductor Corp, CY8C20646A-24LTXI Datasheet - Page 28

• Manufacturer Part Number: CY8C20646A-24LTXI
• Description: MCU 16K FLASH 2K SRAM 48VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CapSense® Controllersr

Specifications of CY8C20646A-24LTXI

• Program Memory Type: FLASH (16 kB)
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Applications: Capacitive Sensing
• Core Processor: M8C
• Controller Series: CY8C20xx6A
• Ram Size: 2K x 8
• Interface: I²C, SPI, USB
• Number Of I /o: 36
• Voltage - Supply: 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8C20x46A
• Core: M8C
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 400 KHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3280-20X66
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 16 KB
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (typ): 1.8/2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: QFN EP
• Pin Count: 48
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Compliant

AC Programming Specifications
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 32. AC Programming Specifications
Document Number: 001-54459 Rev. **
T
T
T
T
F
T
T
T
T
T
T
Symbol
RSCLK
FSCLK
SSCLK
HSCLK
SCLK
ERASEB
WRITE
DSCLK
DSCLK3
DSCLK2
XRST3
SCLK (P1[1])
SDATA (P1[0])
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK 3.6 < Vdd
Data Out Delay from Falling Edge of SCLK 3.0 ≤ Vdd ≤ 3.6
Data Out Delay from Falling Edge of SCLK 1.71 ≤ Vdd ≤ 3.0
External Reset Pulse Width after Power Up Required to enter programming mode
T
RSCLK
Description
T
SSCLK
T
FSCLK
Figure 13. AC Waveform
T
HSCLK
when coming out of sleep
Conditions
CY8C20X36A/46A/66A/96A
T
Min
263
DSCLK
40
40
1
1
0
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
–
–
–
Max
130
20
20
18
25
60
85
–
–
8
–
Page 28 of 38
Units
MHz
ms
ms
ns
ns
ns
ns
ns
ns
ns
μs
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